Commit fa5ce3d1 authored by Robert Richter's avatar Robert Richter Committed by Will Deacon

arm64: errata: Provide macro for major and minor cpu revisions

Definition of cpu ranges are hard to read if the cpu variant is not
zero. Provide MIDR_CPU_VAR_REV() macro to describe the full hardware
revision of a cpu including variant and (minor) revision.
Signed-off-by: default avatarRobert Richter <rrichter@cavium.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent eac8017f
...@@ -56,6 +56,9 @@ ...@@ -56,6 +56,9 @@
(0xf << MIDR_ARCHITECTURE_SHIFT) | \ (0xf << MIDR_ARCHITECTURE_SHIFT) | \
((partnum) << MIDR_PARTNUM_SHIFT)) ((partnum) << MIDR_PARTNUM_SHIFT))
#define MIDR_CPU_VAR_REV(var, rev) \
(((var) << MIDR_VARIANT_SHIFT) | (rev))
#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
MIDR_ARCHITECTURE_MASK) MIDR_ARCHITECTURE_MASK)
......
...@@ -79,8 +79,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ...@@ -79,8 +79,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A57 r0p0 - r1p2 */ /* Cortex-A57 r0p0 - r1p2 */
.desc = "ARM erratum 832075", .desc = "ARM erratum 832075",
.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE, .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
MIDR_RANGE(MIDR_CORTEX_A57, 0x00, MIDR_RANGE(MIDR_CORTEX_A57,
(1 << MIDR_VARIANT_SHIFT) | 2), MIDR_CPU_VAR_REV(0, 0),
MIDR_CPU_VAR_REV(1, 2)),
}, },
#endif #endif
#ifdef CONFIG_ARM64_ERRATUM_834220 #ifdef CONFIG_ARM64_ERRATUM_834220
...@@ -88,8 +89,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ...@@ -88,8 +89,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cortex-A57 r0p0 - r1p2 */ /* Cortex-A57 r0p0 - r1p2 */
.desc = "ARM erratum 834220", .desc = "ARM erratum 834220",
.capability = ARM64_WORKAROUND_834220, .capability = ARM64_WORKAROUND_834220,
MIDR_RANGE(MIDR_CORTEX_A57, 0x00, MIDR_RANGE(MIDR_CORTEX_A57,
(1 << MIDR_VARIANT_SHIFT) | 2), MIDR_CPU_VAR_REV(0, 0),
MIDR_CPU_VAR_REV(1, 2)),
}, },
#endif #endif
#ifdef CONFIG_ARM64_ERRATUM_845719 #ifdef CONFIG_ARM64_ERRATUM_845719
...@@ -113,8 +115,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ...@@ -113,8 +115,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
/* Cavium ThunderX, T88 pass 1.x - 2.1 */ /* Cavium ThunderX, T88 pass 1.x - 2.1 */
.desc = "Cavium erratum 27456", .desc = "Cavium erratum 27456",
.capability = ARM64_WORKAROUND_CAVIUM_27456, .capability = ARM64_WORKAROUND_CAVIUM_27456,
MIDR_RANGE(MIDR_THUNDERX, 0x00, MIDR_RANGE(MIDR_THUNDERX,
(1 << MIDR_VARIANT_SHIFT) | 1), MIDR_CPU_VAR_REV(0, 0),
MIDR_CPU_VAR_REV(1, 1)),
}, },
{ {
/* Cavium ThunderX, T81 pass 1.0 */ /* Cavium ThunderX, T81 pass 1.0 */
......
...@@ -730,13 +730,11 @@ static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, ...@@ -730,13 +730,11 @@ static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry,
static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused) static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
{ {
u32 midr = read_cpuid_id(); u32 midr = read_cpuid_id();
u32 rv_min, rv_max;
/* Cavium ThunderX pass 1.x and 2.x */ /* Cavium ThunderX pass 1.x and 2.x */
rv_min = 0; return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
rv_max = (1 << MIDR_VARIANT_SHIFT) | MIDR_REVISION_MASK; MIDR_CPU_VAR_REV(0, 0),
MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX, rv_min, rv_max);
} }
static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
......
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