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Commit fa62f39d authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
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MIPS: Fix build error due to PTR used in more places 

Use PTR_WD instead of PTR to avoid clashes with other parts.
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent e783362e
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Showing with 185 additions and 185 deletions
arch/mips/include/asm/asm.h
View file @ fa62f39d
...@@ -285,7 +285,7 @@ symbol = value ...@@ -285,7 +285,7 @@ symbol = value
#define PTR_SCALESHIFT 2 #define PTR_SCALESHIFT 2
#define PTR .word #define PTR_WD .word
#define PTRSIZE 4 #define PTRSIZE 4
#define PTRLOG 2 #define PTRLOG 2
#endif #endif
...@@ -310,7 +310,7 @@ symbol = value ...@@ -310,7 +310,7 @@ symbol = value
#define PTR_SCALESHIFT 3 #define PTR_SCALESHIFT 3
#define PTR .dword #define PTR_WD .dword
#define PTRSIZE 8 #define PTRSIZE 8
#define PTRLOG 3 #define PTRLOG 3
#endif #endif
......
arch/mips/include/asm/ftrace.h
View file @ fa62f39d
...@@ -32,7 +32,7 @@ do { \ ...@@ -32,7 +32,7 @@ do { \
".previous\n" \ ".previous\n" \
\ \
".section\t__ex_table,\"a\"\n\t" \ ".section\t__ex_table,\"a\"\n\t" \
STR(PTR) "\t1b, 3b\n\t" \ STR(PTR_WD) "\t1b, 3b\n\t" \
".previous\n" \ ".previous\n" \
\ \
: [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\ : [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\
...@@ -54,7 +54,7 @@ do { \ ...@@ -54,7 +54,7 @@ do { \
".previous\n" \ ".previous\n" \
\ \
".section\t__ex_table,\"a\"\n\t"\ ".section\t__ex_table,\"a\"\n\t"\
STR(PTR) "\t1b, 3b\n\t" \ STR(PTR_WD) "\t1b, 3b\n\t" \
".previous\n" \ ".previous\n" \
\ \
: [tmp_err] "=r" (error) \ : [tmp_err] "=r" (error) \
......
arch/mips/include/asm/r4kcache.h
View file @ fa62f39d
...@@ -119,7 +119,7 @@ static inline void flush_scache_line(unsigned long addr) ...@@ -119,7 +119,7 @@ static inline void flush_scache_line(unsigned long addr)
" j 2b \n" \ " j 2b \n" \
" .previous \n" \ " .previous \n" \
" .section __ex_table,\"a\" \n" \ " .section __ex_table,\"a\" \n" \
" "STR(PTR)" 1b, 3b \n" \ " "STR(PTR_WD)" 1b, 3b \n" \
" .previous" \ " .previous" \
: "+r" (__err) \ : "+r" (__err) \
: "i" (op), "r" (addr), "i" (-EFAULT)); \ : "i" (op), "r" (addr), "i" (-EFAULT)); \
...@@ -142,7 +142,7 @@ static inline void flush_scache_line(unsigned long addr) ...@@ -142,7 +142,7 @@ static inline void flush_scache_line(unsigned long addr)
" j 2b \n" \ " j 2b \n" \
" .previous \n" \ " .previous \n" \
" .section __ex_table,\"a\" \n" \ " .section __ex_table,\"a\" \n" \
" "STR(PTR)" 1b, 3b \n" \ " "STR(PTR_WD)" 1b, 3b \n" \
" .previous" \ " .previous" \
: "+r" (__err) \ : "+r" (__err) \
: "i" (op), "r" (addr), "i" (-EFAULT)); \ : "i" (op), "r" (addr), "i" (-EFAULT)); \
......
arch/mips/include/asm/unaligned-emul.h
View file @ fa62f39d
This diff is collapsed.
arch/mips/kernel/mips-r2-to-r6-emul.c
View file @ fa62f39d
...@@ -1258,10 +1258,10 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -1258,10 +1258,10 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
" j 10b\n" " j 10b\n"
" .previous\n" " .previous\n"
" .section __ex_table,\"a\"\n" " .section __ex_table,\"a\"\n"
STR(PTR) " 1b,8b\n" STR(PTR_WD) " 1b,8b\n"
STR(PTR) " 2b,8b\n" STR(PTR_WD) " 2b,8b\n"
STR(PTR) " 3b,8b\n" STR(PTR_WD) " 3b,8b\n"
STR(PTR) " 4b,8b\n" STR(PTR_WD) " 4b,8b\n"
" .previous\n" " .previous\n"
" .set pop\n" " .set pop\n"
: "+&r"(rt), "=&r"(rs), : "+&r"(rt), "=&r"(rs),
...@@ -1333,10 +1333,10 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -1333,10 +1333,10 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
" j 10b\n" " j 10b\n"
" .previous\n" " .previous\n"
" .section __ex_table,\"a\"\n" " .section __ex_table,\"a\"\n"
STR(PTR) " 1b,8b\n" STR(PTR_WD) " 1b,8b\n"
STR(PTR) " 2b,8b\n" STR(PTR_WD) " 2b,8b\n"
STR(PTR) " 3b,8b\n" STR(PTR_WD) " 3b,8b\n"
STR(PTR) " 4b,8b\n" STR(PTR_WD) " 4b,8b\n"
" .previous\n" " .previous\n"
" .set pop\n" " .set pop\n"
: "+&r"(rt), "=&r"(rs), : "+&r"(rt), "=&r"(rs),
...@@ -1404,10 +1404,10 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -1404,10 +1404,10 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
" j 9b\n" " j 9b\n"
" .previous\n" " .previous\n"
" .section __ex_table,\"a\"\n" " .section __ex_table,\"a\"\n"
STR(PTR) " 1b,8b\n" STR(PTR_WD) " 1b,8b\n"
STR(PTR) " 2b,8b\n" STR(PTR_WD) " 2b,8b\n"
STR(PTR) " 3b,8b\n" STR(PTR_WD) " 3b,8b\n"
STR(PTR) " 4b,8b\n" STR(PTR_WD) " 4b,8b\n"
" .previous\n" " .previous\n"
" .set pop\n" " .set pop\n"
: "+&r"(rt), "=&r"(rs), : "+&r"(rt), "=&r"(rs),
...@@ -1474,10 +1474,10 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -1474,10 +1474,10 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
" j 9b\n" " j 9b\n"
" .previous\n" " .previous\n"
" .section __ex_table,\"a\"\n" " .section __ex_table,\"a\"\n"
STR(PTR) " 1b,8b\n" STR(PTR_WD) " 1b,8b\n"
STR(PTR) " 2b,8b\n" STR(PTR_WD) " 2b,8b\n"
STR(PTR) " 3b,8b\n" STR(PTR_WD) " 3b,8b\n"
STR(PTR) " 4b,8b\n" STR(PTR_WD) " 4b,8b\n"
" .previous\n" " .previous\n"
" .set pop\n" " .set pop\n"
: "+&r"(rt), "=&r"(rs), : "+&r"(rt), "=&r"(rs),
...@@ -1589,14 +1589,14 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -1589,14 +1589,14 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
" j 9b\n" " j 9b\n"
" .previous\n" " .previous\n"
" .section __ex_table,\"a\"\n" " .section __ex_table,\"a\"\n"
STR(PTR) " 1b,8b\n" STR(PTR_WD) " 1b,8b\n"
STR(PTR) " 2b,8b\n" STR(PTR_WD) " 2b,8b\n"
STR(PTR) " 3b,8b\n" STR(PTR_WD) " 3b,8b\n"
STR(PTR) " 4b,8b\n" STR(PTR_WD) " 4b,8b\n"
STR(PTR) " 5b,8b\n" STR(PTR_WD) " 5b,8b\n"
STR(PTR) " 6b,8b\n" STR(PTR_WD) " 6b,8b\n"
STR(PTR) " 7b,8b\n" STR(PTR_WD) " 7b,8b\n"
STR(PTR) " 0b,8b\n" STR(PTR_WD) " 0b,8b\n"
" .previous\n" " .previous\n"
" .set pop\n" " .set pop\n"
: "+&r"(rt), "=&r"(rs), : "+&r"(rt), "=&r"(rs),
...@@ -1708,14 +1708,14 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -1708,14 +1708,14 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
" j 9b\n" " j 9b\n"
" .previous\n" " .previous\n"
" .section __ex_table,\"a\"\n" " .section __ex_table,\"a\"\n"
STR(PTR) " 1b,8b\n" STR(PTR_WD) " 1b,8b\n"
STR(PTR) " 2b,8b\n" STR(PTR_WD) " 2b,8b\n"
STR(PTR) " 3b,8b\n" STR(PTR_WD) " 3b,8b\n"
STR(PTR) " 4b,8b\n" STR(PTR_WD) " 4b,8b\n"
STR(PTR) " 5b,8b\n" STR(PTR_WD) " 5b,8b\n"
STR(PTR) " 6b,8b\n" STR(PTR_WD) " 6b,8b\n"
STR(PTR) " 7b,8b\n" STR(PTR_WD) " 7b,8b\n"
STR(PTR) " 0b,8b\n" STR(PTR_WD) " 0b,8b\n"
" .previous\n" " .previous\n"
" .set pop\n" " .set pop\n"
: "+&r"(rt), "=&r"(rs), : "+&r"(rt), "=&r"(rs),
...@@ -1827,14 +1827,14 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -1827,14 +1827,14 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
" j 9b\n" " j 9b\n"
" .previous\n" " .previous\n"
" .section __ex_table,\"a\"\n" " .section __ex_table,\"a\"\n"
STR(PTR) " 1b,8b\n" STR(PTR_WD) " 1b,8b\n"
STR(PTR) " 2b,8b\n" STR(PTR_WD) " 2b,8b\n"
STR(PTR) " 3b,8b\n" STR(PTR_WD) " 3b,8b\n"
STR(PTR) " 4b,8b\n" STR(PTR_WD) " 4b,8b\n"
STR(PTR) " 5b,8b\n" STR(PTR_WD) " 5b,8b\n"
STR(PTR) " 6b,8b\n" STR(PTR_WD) " 6b,8b\n"
STR(PTR) " 7b,8b\n" STR(PTR_WD) " 7b,8b\n"
STR(PTR) " 0b,8b\n" STR(PTR_WD) " 0b,8b\n"
" .previous\n" " .previous\n"
" .set pop\n" " .set pop\n"
: "+&r"(rt), "=&r"(rs), : "+&r"(rt), "=&r"(rs),
...@@ -1945,14 +1945,14 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -1945,14 +1945,14 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
" j 9b\n" " j 9b\n"
" .previous\n" " .previous\n"
" .section __ex_table,\"a\"\n" " .section __ex_table,\"a\"\n"
STR(PTR) " 1b,8b\n" STR(PTR_WD) " 1b,8b\n"
STR(PTR) " 2b,8b\n" STR(PTR_WD) " 2b,8b\n"
STR(PTR) " 3b,8b\n" STR(PTR_WD) " 3b,8b\n"
STR(PTR) " 4b,8b\n" STR(PTR_WD) " 4b,8b\n"
STR(PTR) " 5b,8b\n" STR(PTR_WD) " 5b,8b\n"
STR(PTR) " 6b,8b\n" STR(PTR_WD) " 6b,8b\n"
STR(PTR) " 7b,8b\n" STR(PTR_WD) " 7b,8b\n"
STR(PTR) " 0b,8b\n" STR(PTR_WD) " 0b,8b\n"
" .previous\n" " .previous\n"
" .set pop\n" " .set pop\n"
: "+&r"(rt), "=&r"(rs), : "+&r"(rt), "=&r"(rs),
...@@ -2007,7 +2007,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -2007,7 +2007,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
"j 2b\n" "j 2b\n"
".previous\n" ".previous\n"
".section __ex_table,\"a\"\n" ".section __ex_table,\"a\"\n"
STR(PTR) " 1b,3b\n" STR(PTR_WD) " 1b,3b\n"
".previous\n" ".previous\n"
: "=&r"(res), "+&r"(err) : "=&r"(res), "+&r"(err)
: "r"(vaddr), "i"(SIGSEGV) : "r"(vaddr), "i"(SIGSEGV)
...@@ -2065,7 +2065,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -2065,7 +2065,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
"j 2b\n" "j 2b\n"
".previous\n" ".previous\n"
".section __ex_table,\"a\"\n" ".section __ex_table,\"a\"\n"
STR(PTR) " 1b,3b\n" STR(PTR_WD) " 1b,3b\n"
".previous\n" ".previous\n"
: "+&r"(res), "+&r"(err) : "+&r"(res), "+&r"(err)
: "r"(vaddr), "i"(SIGSEGV)); : "r"(vaddr), "i"(SIGSEGV));
...@@ -2126,7 +2126,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -2126,7 +2126,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
"j 2b\n" "j 2b\n"
".previous\n" ".previous\n"
".section __ex_table,\"a\"\n" ".section __ex_table,\"a\"\n"
STR(PTR) " 1b,3b\n" STR(PTR_WD) " 1b,3b\n"
".previous\n" ".previous\n"
: "=&r"(res), "+&r"(err) : "=&r"(res), "+&r"(err)
: "r"(vaddr), "i"(SIGSEGV) : "r"(vaddr), "i"(SIGSEGV)
...@@ -2189,7 +2189,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31) ...@@ -2189,7 +2189,7 @@ int mipsr2_decoder(struct pt_regs *regs, u32 inst, unsigned long *fcr31)
"j 2b\n" "j 2b\n"
".previous\n" ".previous\n"
".section __ex_table,\"a\"\n" ".section __ex_table,\"a\"\n"
STR(PTR) " 1b,3b\n" STR(PTR_WD) " 1b,3b\n"
".previous\n" ".previous\n"
: "+&r"(res), "+&r"(err) : "+&r"(res), "+&r"(err)
: "r"(vaddr), "i"(SIGSEGV)); : "r"(vaddr), "i"(SIGSEGV));
......
arch/mips/kernel/r2300_fpu.S
View file @ fa62f39d
...@@ -23,14 +23,14 @@ ...@@ -23,14 +23,14 @@
#define EX(a,b) \ #define EX(a,b) \
9: a,##b; \ 9: a,##b; \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b,fault; \ PTR_WD 9b,fault; \
.previous .previous
#define EX2(a,b) \ #define EX2(a,b) \
9: a,##b; \ 9: a,##b; \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b,fault; \ PTR_WD 9b,fault; \
PTR 9b+4,fault; \ PTR_WD 9b+4,fault; \
.previous .previous
.set mips1 .set mips1
......
arch/mips/kernel/r4k_fpu.S
View file @ fa62f39d
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
.ex\@: \insn \reg, \src .ex\@: \insn \reg, \src
.set pop .set pop
.section __ex_table,"a" .section __ex_table,"a"
PTR .ex\@, fault PTR_WD .ex\@, fault
.previous .previous
.endm .endm
......
arch/mips/kernel/relocate_kernel.S
View file @ fa62f39d
...@@ -147,10 +147,10 @@ LEAF(kexec_smp_wait) ...@@ -147,10 +147,10 @@ LEAF(kexec_smp_wait)
kexec_args: kexec_args:
EXPORT(kexec_args) EXPORT(kexec_args)
arg0: PTR 0x0 arg0: PTR_WD 0x0
arg1: PTR 0x0 arg1: PTR_WD 0x0
arg2: PTR 0x0 arg2: PTR_WD 0x0
arg3: PTR 0x0 arg3: PTR_WD 0x0
.size kexec_args,PTRSIZE*4 .size kexec_args,PTRSIZE*4
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
...@@ -161,10 +161,10 @@ arg3: PTR 0x0 ...@@ -161,10 +161,10 @@ arg3: PTR 0x0
*/ */
secondary_kexec_args: secondary_kexec_args:
EXPORT(secondary_kexec_args) EXPORT(secondary_kexec_args)
s_arg0: PTR 0x0 s_arg0: PTR_WD 0x0
s_arg1: PTR 0x0 s_arg1: PTR_WD 0x0
s_arg2: PTR 0x0 s_arg2: PTR_WD 0x0
s_arg3: PTR 0x0 s_arg3: PTR_WD 0x0
.size secondary_kexec_args,PTRSIZE*4 .size secondary_kexec_args,PTRSIZE*4
kexec_flag: kexec_flag:
LONG 0x1 LONG 0x1
...@@ -173,17 +173,17 @@ kexec_flag: ...@@ -173,17 +173,17 @@ kexec_flag:
kexec_start_address: kexec_start_address:
EXPORT(kexec_start_address) EXPORT(kexec_start_address)
PTR 0x0 PTR_WD 0x0
.size kexec_start_address, PTRSIZE .size kexec_start_address, PTRSIZE
kexec_indirection_page: kexec_indirection_page:
EXPORT(kexec_indirection_page) EXPORT(kexec_indirection_page)
PTR 0 PTR_WD 0
.size kexec_indirection_page, PTRSIZE .size kexec_indirection_page, PTRSIZE
relocate_new_kernel_end: relocate_new_kernel_end:
relocate_new_kernel_size: relocate_new_kernel_size:
EXPORT(relocate_new_kernel_size) EXPORT(relocate_new_kernel_size)
PTR relocate_new_kernel_end - relocate_new_kernel PTR_WD relocate_new_kernel_end - relocate_new_kernel
.size relocate_new_kernel_size, PTRSIZE .size relocate_new_kernel_size, PTRSIZE
arch/mips/kernel/scall32-o32.S
View file @ fa62f39d
...@@ -72,10 +72,10 @@ loads_done: ...@@ -72,10 +72,10 @@ loads_done:
.set pop .set pop
.section __ex_table,"a" .section __ex_table,"a"
PTR load_a4, bad_stack_a4 PTR_WD load_a4, bad_stack_a4
PTR load_a5, bad_stack_a5 PTR_WD load_a5, bad_stack_a5
PTR load_a6, bad_stack_a6 PTR_WD load_a6, bad_stack_a6
PTR load_a7, bad_stack_a7 PTR_WD load_a7, bad_stack_a7
.previous .previous
lw t0, TI_FLAGS($28) # syscall tracing enabled? lw t0, TI_FLAGS($28) # syscall tracing enabled?
...@@ -216,7 +216,7 @@ einval: li v0, -ENOSYS ...@@ -216,7 +216,7 @@ einval: li v0, -ENOSYS
#endif /* CONFIG_MIPS_MT_FPAFF */ #endif /* CONFIG_MIPS_MT_FPAFF */
#define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, native) #define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, native)
#define __SYSCALL(nr, entry) PTR entry #define __SYSCALL(nr, entry) PTR_WD entry
.align 2 .align 2
.type sys_call_table, @object .type sys_call_table, @object
EXPORT(sys_call_table) EXPORT(sys_call_table)
......
arch/mips/kernel/scall64-n32.S
View file @ fa62f39d
...@@ -101,7 +101,7 @@ not_n32_scall: ...@@ -101,7 +101,7 @@ not_n32_scall:
END(handle_sysn32) END(handle_sysn32)
#define __SYSCALL(nr, entry) PTR entry #define __SYSCALL(nr, entry) PTR_WD entry
.type sysn32_call_table, @object .type sysn32_call_table, @object
EXPORT(sysn32_call_table) EXPORT(sysn32_call_table)
#include <asm/syscall_table_n32.h> #include <asm/syscall_table_n32.h>
arch/mips/kernel/scall64-n64.S
View file @ fa62f39d
...@@ -109,7 +109,7 @@ illegal_syscall: ...@@ -109,7 +109,7 @@ illegal_syscall:
j n64_syscall_exit j n64_syscall_exit
END(handle_sys64) END(handle_sys64)
#define __SYSCALL(nr, entry) PTR entry #define __SYSCALL(nr, entry) PTR_WD entry
.align 3 .align 3
.type sys_call_table, @object .type sys_call_table, @object
EXPORT(sys_call_table) EXPORT(sys_call_table)
......
arch/mips/kernel/scall64-o32.S
View file @ fa62f39d
...@@ -73,10 +73,10 @@ load_a7: lw a7, 28(t0) # argument #8 from usp ...@@ -73,10 +73,10 @@ load_a7: lw a7, 28(t0) # argument #8 from usp
loads_done: loads_done:
.section __ex_table,"a" .section __ex_table,"a"
PTR load_a4, bad_stack_a4 PTR_WD load_a4, bad_stack_a4
PTR load_a5, bad_stack_a5 PTR_WD load_a5, bad_stack_a5
PTR load_a6, bad_stack_a6 PTR_WD load_a6, bad_stack_a6
PTR load_a7, bad_stack_a7 PTR_WD load_a7, bad_stack_a7
.previous .previous
li t1, _TIF_WORK_SYSCALL_ENTRY li t1, _TIF_WORK_SYSCALL_ENTRY
...@@ -214,7 +214,7 @@ einval: li v0, -ENOSYS ...@@ -214,7 +214,7 @@ einval: li v0, -ENOSYS
END(sys32_syscall) END(sys32_syscall)
#define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, compat) #define __SYSCALL_WITH_COMPAT(nr, native, compat) __SYSCALL(nr, compat)
#define __SYSCALL(nr, entry) PTR entry #define __SYSCALL(nr, entry) PTR_WD entry
.align 3 .align 3
.type sys32_call_table,@object .type sys32_call_table,@object
EXPORT(sys32_call_table) EXPORT(sys32_call_table)
......
arch/mips/kernel/syscall.c
View file @ fa62f39d
...@@ -122,8 +122,8 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) ...@@ -122,8 +122,8 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
" j 3b \n" " j 3b \n"
" .previous \n" " .previous \n"
" .section __ex_table,\"a\" \n" " .section __ex_table,\"a\" \n"
" "STR(PTR)" 1b, 4b \n" " "STR(PTR_WD)" 1b, 4b \n"
" "STR(PTR)" 2b, 4b \n" " "STR(PTR_WD)" 2b, 4b \n"
" .previous \n" " .previous \n"
" .set pop \n" " .set pop \n"
: [old] "=&r" (old), : [old] "=&r" (old),
...@@ -152,8 +152,8 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) ...@@ -152,8 +152,8 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new)
" j 3b \n" " j 3b \n"
" .previous \n" " .previous \n"
" .section __ex_table,\"a\" \n" " .section __ex_table,\"a\" \n"
" "STR(PTR)" 1b, 5b \n" " "STR(PTR_WD)" 1b, 5b \n"
" "STR(PTR)" 2b, 5b \n" " "STR(PTR_WD)" 2b, 5b \n"
" .previous \n" " .previous \n"
" .set pop \n" " .set pop \n"
: [old] "=&r" (old), : [old] "=&r" (old),
......
arch/mips/lib/csum_partial.S
View file @ fa62f39d
...@@ -347,7 +347,7 @@ EXPORT_SYMBOL(csum_partial) ...@@ -347,7 +347,7 @@ EXPORT_SYMBOL(csum_partial)
.if \mode == LEGACY_MODE; \ .if \mode == LEGACY_MODE; \
9: insn reg, addr; \ 9: insn reg, addr; \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b, .L_exc; \ PTR_WD 9b, .L_exc; \
.previous; \ .previous; \
/* This is enabled in EVA mode */ \ /* This is enabled in EVA mode */ \
.else; \ .else; \
...@@ -356,7 +356,7 @@ EXPORT_SYMBOL(csum_partial) ...@@ -356,7 +356,7 @@ EXPORT_SYMBOL(csum_partial)
((\to == USEROP) && (type == ST_INSN)); \ ((\to == USEROP) && (type == ST_INSN)); \
9: __BUILD_EVA_INSN(insn##e, reg, addr); \ 9: __BUILD_EVA_INSN(insn##e, reg, addr); \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b, .L_exc; \ PTR_WD 9b, .L_exc; \
.previous; \ .previous; \
.else; \ .else; \
/* EVA without exception */ \ /* EVA without exception */ \
......
arch/mips/lib/memcpy.S
View file @ fa62f39d
...@@ -116,7 +116,7 @@ ...@@ -116,7 +116,7 @@
.if \mode == LEGACY_MODE; \ .if \mode == LEGACY_MODE; \
9: insn reg, addr; \ 9: insn reg, addr; \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b, handler; \ PTR_WD 9b, handler; \
.previous; \ .previous; \
/* This is assembled in EVA mode */ \ /* This is assembled in EVA mode */ \
.else; \ .else; \
...@@ -125,7 +125,7 @@ ...@@ -125,7 +125,7 @@
((\to == USEROP) && (type == ST_INSN)); \ ((\to == USEROP) && (type == ST_INSN)); \
9: __BUILD_EVA_INSN(insn##e, reg, addr); \ 9: __BUILD_EVA_INSN(insn##e, reg, addr); \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b, handler; \ PTR_WD 9b, handler; \
.previous; \ .previous; \
.else; \ .else; \
/* \ /* \
......
arch/mips/lib/memset.S
View file @ fa62f39d
...@@ -52,7 +52,7 @@ ...@@ -52,7 +52,7 @@
9: ___BUILD_EVA_INSN(insn, reg, addr); \ 9: ___BUILD_EVA_INSN(insn, reg, addr); \
.endif; \ .endif; \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b, handler; \ PTR_WD 9b, handler; \
.previous .previous
.macro f_fill64 dst, offset, val, fixup, mode .macro f_fill64 dst, offset, val, fixup, mode
......
arch/mips/lib/strncpy_user.S
View file @ fa62f39d
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
#define EX(insn,reg,addr,handler) \ #define EX(insn,reg,addr,handler) \
9: insn reg, addr; \ 9: insn reg, addr; \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b, handler; \ PTR_WD 9b, handler; \
.previous .previous
/* /*
...@@ -59,7 +59,7 @@ LEAF(__strncpy_from_user_asm) ...@@ -59,7 +59,7 @@ LEAF(__strncpy_from_user_asm)
jr ra jr ra
.section __ex_table,"a" .section __ex_table,"a"
PTR 1b, .Lfault PTR_WD 1b, .Lfault
.previous .previous
EXPORT_SYMBOL(__strncpy_from_user_asm) EXPORT_SYMBOL(__strncpy_from_user_asm)
arch/mips/lib/strnlen_user.S
View file @ fa62f39d
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
#define EX(insn,reg,addr,handler) \ #define EX(insn,reg,addr,handler) \
9: insn reg, addr; \ 9: insn reg, addr; \
.section __ex_table,"a"; \ .section __ex_table,"a"; \
PTR 9b, handler; \ PTR_WD 9b, handler; \
.previous .previous
/* /*
......
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