Commit fb53905c authored by Kalle Valo's avatar Kalle Valo

Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git

ath.git patches for 4.13. Major changes:

ath10k

* add initial SDIO support (still work in progress)
parents a1ad7198 b01c9e32
......@@ -22,6 +22,13 @@ config ATH10K_AHB
---help---
This module adds support for AHB bus
config ATH10K_SDIO
tristate "Atheros ath10k SDIO support (EXPERIMENTAL)"
depends on ATH10K && MMC
---help---
This module adds experimental support for SDIO/MMC bus. Currently
work in progress and will not fully work.
config ATH10K_DEBUG
bool "Atheros ath10k debugging"
depends on ATH10K
......
......@@ -27,5 +27,8 @@ ath10k_pci-y += pci.o \
ath10k_pci-$(CONFIG_ATH10K_AHB) += ahb.o
obj-$(CONFIG_ATH10K_SDIO) += ath10k_sdio.o
ath10k_sdio-y += sdio.o
# for tracing framework to find trace.h
CFLAGS_trace.o := -I$(src)
......@@ -97,6 +97,77 @@ int ath10k_bmi_get_target_info(struct ath10k *ar,
return 0;
}
#define TARGET_VERSION_SENTINAL 0xffffffffu
int ath10k_bmi_get_target_info_sdio(struct ath10k *ar,
struct bmi_target_info *target_info)
{
struct bmi_cmd cmd;
union bmi_resp resp;
u32 cmdlen = sizeof(cmd.id) + sizeof(cmd.get_target_info);
u32 resplen, ver_len;
__le32 tmp;
int ret;
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi get target info SDIO\n");
if (ar->bmi.done_sent) {
ath10k_warn(ar, "BMI Get Target Info Command disallowed\n");
return -EBUSY;
}
cmd.id = __cpu_to_le32(BMI_GET_TARGET_INFO);
/* Step 1: Read 4 bytes of the target info and check if it is
* the special sentinal version word or the first word in the
* version response.
*/
resplen = sizeof(u32);
ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, cmdlen, &tmp, &resplen);
if (ret) {
ath10k_warn(ar, "unable to read from device\n");
return ret;
}
/* Some SDIO boards have a special sentinal byte before the real
* version response.
*/
if (__le32_to_cpu(tmp) == TARGET_VERSION_SENTINAL) {
/* Step 1b: Read the version length */
resplen = sizeof(u32);
ret = ath10k_hif_exchange_bmi_msg(ar, NULL, 0, &tmp,
&resplen);
if (ret) {
ath10k_warn(ar, "unable to read from device\n");
return ret;
}
}
ver_len = __le32_to_cpu(tmp);
/* Step 2: Check the target info length */
if (ver_len != sizeof(resp.get_target_info)) {
ath10k_warn(ar, "Unexpected target info len: %u. Expected: %zu\n",
ver_len, sizeof(resp.get_target_info));
return -EINVAL;
}
/* Step 3: Read the rest of the version response */
resplen = sizeof(resp.get_target_info) - sizeof(u32);
ret = ath10k_hif_exchange_bmi_msg(ar, NULL, 0,
&resp.get_target_info.version,
&resplen);
if (ret) {
ath10k_warn(ar, "unable to read from device\n");
return ret;
}
target_info->version = __le32_to_cpu(resp.get_target_info.version);
target_info->type = __le32_to_cpu(resp.get_target_info.type);
return 0;
}
int ath10k_bmi_read_memory(struct ath10k *ar,
u32 address, void *buffer, u32 length)
{
......
......@@ -198,6 +198,8 @@ void ath10k_bmi_start(struct ath10k *ar);
int ath10k_bmi_done(struct ath10k *ar);
int ath10k_bmi_get_target_info(struct ath10k *ar,
struct bmi_target_info *target_info);
int ath10k_bmi_get_target_info_sdio(struct ath10k *ar,
struct bmi_target_info *target_info);
int ath10k_bmi_read_memory(struct ath10k *ar, u32 address,
void *buffer, u32 length);
int ath10k_bmi_write_memory(struct ath10k *ar, u32 address,
......
......@@ -389,6 +389,21 @@ static void ath10k_send_suspend_complete(struct ath10k *ar)
complete(&ar->target_suspend);
}
static void ath10k_init_sdio(struct ath10k *ar)
{
u32 param = 0;
ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256);
ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
ath10k_bmi_read32(ar, hi_acs_flags, &param);
param |= (HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET |
HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET |
HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE);
ath10k_bmi_write32(ar, hi_acs_flags, param);
}
static int ath10k_init_configure_target(struct ath10k *ar)
{
u32 param_host;
......@@ -1395,7 +1410,18 @@ int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
size_t fw_name_len, int fw_api)
{
scnprintf(fw_name, fw_name_len, "%s-%d.bin", ATH10K_FW_FILE_BASE, fw_api);
switch (ar->hif.bus) {
case ATH10K_BUS_SDIO:
scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin",
ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus),
fw_api);
break;
case ATH10K_BUS_PCI:
case ATH10K_BUS_AHB:
scnprintf(fw_name, fw_name_len, "%s-%d.bin",
ATH10K_FW_FILE_BASE, fw_api);
break;
}
}
static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
......@@ -1953,6 +1979,9 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
if (status)
goto err;
if (ar->hif.bus == ATH10K_BUS_SDIO)
ath10k_init_sdio(ar);
ar->htc.htc_ops.target_send_suspend_complete =
ath10k_send_suspend_complete;
......@@ -2200,7 +2229,10 @@ static int ath10k_core_probe_fw(struct ath10k *ar)
}
memset(&target_info, 0, sizeof(target_info));
ret = ath10k_bmi_get_target_info(ar, &target_info);
if (ar->hif.bus == ATH10K_BUS_SDIO)
ret = ath10k_bmi_get_target_info_sdio(ar, &target_info);
else
ret = ath10k_bmi_get_target_info(ar, &target_info);
if (ret) {
ath10k_err(ar, "could not get target info (%d)\n", ret);
goto err_power_down;
......
......@@ -91,6 +91,7 @@ struct ath10k;
enum ath10k_bus {
ATH10K_BUS_PCI,
ATH10K_BUS_AHB,
ATH10K_BUS_SDIO,
};
static inline const char *ath10k_bus_str(enum ath10k_bus bus)
......@@ -100,6 +101,8 @@ static inline const char *ath10k_bus_str(enum ath10k_bus bus)
return "pci";
case ATH10K_BUS_AHB:
return "ahb";
case ATH10K_BUS_SDIO:
return "sdio";
}
return "unknown";
......
......@@ -625,17 +625,21 @@ static ssize_t ath10k_write_simulate_fw_crash(struct file *file,
size_t count, loff_t *ppos)
{
struct ath10k *ar = file->private_data;
char buf[32];
char buf[32] = {0};
ssize_t rc;
int ret;
simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count);
/* filter partial writes and invalid commands */
if (*ppos != 0 || count >= sizeof(buf) || count == 0)
return -EINVAL;
/* make sure that buf is null terminated */
buf[sizeof(buf) - 1] = 0;
rc = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count);
if (rc < 0)
return rc;
/* drop the possible '\n' from the end */
if (buf[count - 1] == '\n')
buf[count - 1] = 0;
if (buf[*ppos - 1] == '\n')
buf[*ppos - 1] = '\0';
mutex_lock(&ar->conf_mutex);
......
......@@ -38,6 +38,8 @@ enum ath10k_debug_mask {
ATH10K_DBG_WMI_PRINT = 0x00002000,
ATH10K_DBG_PCI_PS = 0x00004000,
ATH10K_DBG_AHB = 0x00008000,
ATH10K_DBG_SDIO = 0x00010000,
ATH10K_DBG_SDIO_DUMP = 0x00020000,
ATH10K_DBG_ANY = 0xffffffff,
};
......
This diff is collapsed.
......@@ -50,6 +50,8 @@ struct ath10k;
* 4-byte aligned.
*/
#define HTC_HOST_MAX_MSG_PER_BUNDLE 8
enum ath10k_htc_tx_flags {
ATH10K_HTC_FLAG_NEED_CREDIT_UPDATE = 0x01,
ATH10K_HTC_FLAG_SEND_BUNDLE = 0x02
......@@ -110,6 +112,10 @@ enum ath10k_htc_conn_svc_status {
ATH10K_HTC_CONN_SVC_STATUS_NO_MORE_EP = 4
};
enum ath10k_htc_setup_complete_flags {
ATH10K_HTC_SETUP_COMPLETE_FLAGS_RX_BNDL_EN = 1
};
struct ath10k_ath10k_htc_msg_hdr {
__le16 message_id; /* @enum htc_message_id */
} __packed;
......@@ -174,8 +180,10 @@ struct ath10k_htc_msg {
} __packed __aligned(4);
enum ath10k_ath10k_htc_record_id {
ATH10K_HTC_RECORD_NULL = 0,
ATH10K_HTC_RECORD_CREDITS = 1
ATH10K_HTC_RECORD_NULL = 0,
ATH10K_HTC_RECORD_CREDITS = 1,
ATH10K_HTC_RECORD_LOOKAHEAD = 2,
ATH10K_HTC_RECORD_LOOKAHEAD_BUNDLE = 3,
};
struct ath10k_ath10k_htc_record_hdr {
......@@ -192,10 +200,28 @@ struct ath10k_htc_credit_report {
u8 pad1;
} __packed;
struct ath10k_htc_lookahead_report {
u8 pre_valid;
u8 pad0;
u8 pad1;
u8 pad2;
u8 lookahead[4];
u8 post_valid;
u8 pad3;
u8 pad4;
u8 pad5;
} __packed;
struct ath10k_htc_lookahead_bundle {
u8 lookahead[4];
} __packed;
struct ath10k_htc_record {
struct ath10k_ath10k_htc_record_hdr hdr;
union {
struct ath10k_htc_credit_report credit_report[0];
struct ath10k_htc_lookahead_report lookahead_report[0];
struct ath10k_htc_lookahead_bundle lookahead_bundle[0];
u8 pauload[0];
};
} __packed __aligned(4);
......@@ -338,6 +364,7 @@ struct ath10k_htc {
int total_transmit_credits;
int target_credit_size;
u8 max_msgs_per_htc_bundle;
};
int ath10k_htc_init(struct ath10k *ar);
......@@ -351,5 +378,13 @@ int ath10k_htc_send(struct ath10k_htc *htc, enum ath10k_htc_ep_id eid,
struct sk_buff *ath10k_htc_alloc_skb(struct ath10k *ar, int size);
void ath10k_htc_tx_completion_handler(struct ath10k *ar, struct sk_buff *skb);
void ath10k_htc_rx_completion_handler(struct ath10k *ar, struct sk_buff *skb);
void ath10k_htc_notify_tx_completion(struct ath10k_htc_ep *ep,
struct sk_buff *skb);
int ath10k_htc_process_trailer(struct ath10k_htc *htc,
u8 *buffer,
int length,
enum ath10k_htc_ep_id src_eid,
void *next_lookaheads,
int *next_lookaheads_len);
#endif
......@@ -863,6 +863,59 @@ ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw,
#define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000
#define QCA9887_EEPROM_ADDR_LO_LSB 16
#define MBOX_RESET_CONTROL_ADDRESS 0x00000000
#define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800
#define MBOX_HOST_INT_STATUS_ERROR_LSB 7
#define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080
#define MBOX_HOST_INT_STATUS_CPU_LSB 6
#define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040
#define MBOX_HOST_INT_STATUS_COUNTER_LSB 4
#define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010
#define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801
#define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802
#define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2
#define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
#define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803
#define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0
#define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
#define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805
#define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828
#define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7
#define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080
#define MBOX_INT_STATUS_ENABLE_CPU_LSB 6
#define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040
#define MBOX_INT_STATUS_ENABLE_INT_LSB 5
#define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020
#define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4
#define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0
#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
#define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819
#define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0
#define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a
#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
#define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b
#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define MBOX_COUNT_ADDRESS 0x00000820
#define MBOX_COUNT_DEC_ADDRESS 0x00000840
#define MBOX_WINDOW_DATA_ADDRESS 0x00000874
#define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878
#define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c
#define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883
#define MBOX_CPU_DBG_ADDRESS 0x00000884
#define MBOX_RTC_BASE_ADDRESS 0x00000000
#define MBOX_GPIO_BASE_ADDRESS 0x00005000
#define MBOX_MBOX_BASE_ADDRESS 0x00008000
#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
/* Register definitions for first generation ath10k cards. These cards include
......
This diff is collapsed.
/*
* Copyright (c) 2004-2011 Atheros Communications Inc.
* Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
* Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _SDIO_H_
#define _SDIO_H_
#define ATH10K_HIF_MBOX_BLOCK_SIZE 256
#define QCA_MANUFACTURER_ID_BASE GENMASK(11, 8)
#define QCA_MANUFACTURER_ID_AR6005_BASE 0x5
#define QCA_MANUFACTURER_ID_QCA9377_BASE 0x7
#define QCA_SDIO_ID_AR6005_BASE 0x500
#define QCA_SDIO_ID_QCA9377_BASE 0x700
#define QCA_MANUFACTURER_ID_REV_MASK 0x00FF
#define QCA_MANUFACTURER_CODE 0x271 /* Qualcomm/Atheros */
#define ATH10K_SDIO_MAX_BUFFER_SIZE 4096 /*Unsure of this constant*/
/* Mailbox address in SDIO address space */
#define ATH10K_HIF_MBOX_BASE_ADDR 0x1000
#define ATH10K_HIF_MBOX_WIDTH 0x800
#define ATH10K_HIF_MBOX_TOT_WIDTH \
(ATH10K_HIF_MBOX_NUM_MAX * ATH10K_HIF_MBOX_WIDTH)
#define ATH10K_HIF_MBOX0_EXT_BASE_ADDR 0x5000
#define ATH10K_HIF_MBOX0_EXT_WIDTH (36 * 1024)
#define ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0 (56 * 1024)
#define ATH10K_HIF_MBOX1_EXT_WIDTH (36 * 1024)
#define ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE (2 * 1024)
#define ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH \
(ATH10K_SDIO_MAX_BUFFER_SIZE - sizeof(struct ath10k_htc_hdr))
#define ATH10K_HIF_MBOX_NUM_MAX 4
#define ATH10K_SDIO_BUS_REQUEST_MAX_NUM 64
#define ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ (100 * HZ)
/* HTC runs over mailbox 0 */
#define ATH10K_HTC_MAILBOX 0
#define ATH10K_HTC_MAILBOX_MASK BIT(ATH10K_HTC_MAILBOX)
/* GMBOX addresses */
#define ATH10K_HIF_GMBOX_BASE_ADDR 0x7000
#define ATH10K_HIF_GMBOX_WIDTH 0x4000
/* Modified versions of the sdio.h macros.
* The macros in sdio.h can't be used easily with the FIELD_{PREP|GET}
* macros in bitfield.h, so we define our own macros here.
*/
#define ATH10K_SDIO_DRIVE_DTSX_MASK \
(SDIO_DRIVE_DTSx_MASK << SDIO_DRIVE_DTSx_SHIFT)
#define ATH10K_SDIO_DRIVE_DTSX_TYPE_B 0
#define ATH10K_SDIO_DRIVE_DTSX_TYPE_A 1
#define ATH10K_SDIO_DRIVE_DTSX_TYPE_C 2
#define ATH10K_SDIO_DRIVE_DTSX_TYPE_D 3
/* SDIO CCCR register definitions */
#define CCCR_SDIO_IRQ_MODE_REG 0xF0
#define CCCR_SDIO_IRQ_MODE_REG_SDIO3 0x16
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR 0xF2
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A 0x02
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C 0x04
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D 0x08
#define CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS 0xF0
#define CCCR_SDIO_ASYNC_INT_DELAY_MASK 0xC0
/* mode to enable special 4-bit interrupt assertion without clock */
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ BIT(0)
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3 BIT(1)
#define ATH10K_SDIO_TARGET_DEBUG_INTR_MASK 0x01
/* The theoretical maximum number of RX messages that can be fetched
* from the mbox interrupt handler in one loop is derived in the following
* way:
*
* Let's assume that each packet in a bundle of the maximum bundle size
* (HTC_HOST_MAX_MSG_PER_BUNDLE) has the HTC header bundle count set
* to the maximum value (HTC_HOST_MAX_MSG_PER_BUNDLE).
*
* in this case the driver must allocate
* (HTC_HOST_MAX_MSG_PER_BUNDLE * HTC_HOST_MAX_MSG_PER_BUNDLE) skb's.
*/
#define ATH10K_SDIO_MAX_RX_MSGS \
(HTC_HOST_MAX_MSG_PER_BUNDLE * HTC_HOST_MAX_MSG_PER_BUNDLE)
#define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL 0x00000868u
#define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF 0xFFFEFFFF
#define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON 0x10000
struct ath10k_sdio_bus_request {
struct list_head list;
/* sdio address */
u32 address;
struct sk_buff *skb;
enum ath10k_htc_ep_id eid;
int status;
/* Specifies if the current request is an HTC message.
* If not, the eid is not applicable an the TX completion handler
* associated with the endpoint will not be invoked.
*/
bool htc_msg;
/* Completion that (if set) will be invoked for non HTC requests
* (htc_msg == false) when the request has been processed.
*/
struct completion *comp;
};
struct ath10k_sdio_rx_data {
struct sk_buff *skb;
size_t alloc_len;
size_t act_len;
enum ath10k_htc_ep_id eid;
bool part_of_bundle;
bool last_in_bundle;
bool trailer_only;
int status;
};
struct ath10k_sdio_irq_proc_regs {
u8 host_int_status;
u8 cpu_int_status;
u8 error_int_status;
u8 counter_int_status;
u8 mbox_frame;
u8 rx_lookahead_valid;
u8 host_int_status2;
u8 gmbox_rx_avail;
__le32 rx_lookahead[2];
__le32 rx_gmbox_lookahead_alias[2];
};
struct ath10k_sdio_irq_enable_regs {
u8 int_status_en;
u8 cpu_int_status_en;
u8 err_int_status_en;
u8 cntr_int_status_en;
};
struct ath10k_sdio_irq_data {
/* protects irq_proc_reg and irq_en_reg below.
* We use a mutex here and not a spinlock since we will have the
* mutex locked while calling the sdio_memcpy_ functions.
* These function require non atomic context, and hence, spinlocks
* can be held while calling these functions.
*/
struct mutex mtx;
struct ath10k_sdio_irq_proc_regs *irq_proc_reg;
struct ath10k_sdio_irq_enable_regs *irq_en_reg;
};
struct ath10k_mbox_ext_info {
u32 htc_ext_addr;
u32 htc_ext_sz;
};
struct ath10k_mbox_info {
u32 htc_addr;
struct ath10k_mbox_ext_info ext_info[2];
u32 block_size;
u32 block_mask;
u32 gmbox_addr;
u32 gmbox_sz;
};
struct ath10k_sdio {
struct sdio_func *func;
struct ath10k_mbox_info mbox_info;
bool swap_mbox;
u32 mbox_addr[ATH10K_HTC_EP_COUNT];
u32 mbox_size[ATH10K_HTC_EP_COUNT];
/* available bus requests */
struct ath10k_sdio_bus_request bus_req[ATH10K_SDIO_BUS_REQUEST_MAX_NUM];
/* free list of bus requests */
struct list_head bus_req_freeq;
/* protects access to bus_req_freeq */
spinlock_t lock;
struct ath10k_sdio_rx_data rx_pkts[ATH10K_SDIO_MAX_RX_MSGS];
size_t n_rx_pkts;
struct ath10k *ar;
struct ath10k_sdio_irq_data irq_data;
/* temporary buffer for BMI requests */
u8 *bmi_buf;
wait_queue_head_t irq_wq;
bool is_disabled;
struct workqueue_struct *workqueue;
struct work_struct wr_async_work;
struct list_head wr_asyncq;
/* protects access to wr_asyncq */
spinlock_t wr_async_lock;
};
static inline struct ath10k_sdio *ath10k_sdio_priv(struct ath10k *ar)
{
return (struct ath10k_sdio *)ar->drv_priv;
}
#endif
......@@ -205,6 +205,24 @@ struct host_interest {
*/
/* Bit 1 - unused */
u32 hi_fw_swap; /* 0x104 */
/* global arenas pointer address, used by host driver debug */
u32 hi_dynamic_mem_arenas_addr; /* 0x108 */
/* allocated bytes of DRAM use by allocated */
u32 hi_dynamic_mem_allocated; /* 0x10C */
/* remaining bytes of DRAM */
u32 hi_dynamic_mem_remaining; /* 0x110 */
/* memory track count, configured by host */
u32 hi_dynamic_mem_track_max; /* 0x114 */
/* minidump buffer */
u32 hi_minidump; /* 0x118 */
/* bdata's sig and key addr */
u32 hi_bd_sig_key; /* 0x11c */
} __packed;
#define HI_ITEM(item) offsetof(struct host_interest, item)
......@@ -319,6 +337,12 @@ struct host_interest {
#define HI_ACS_FLAGS_USE_WWAN (1 << 1)
/* Use test VAP */
#define HI_ACS_FLAGS_TEST_VAP (1 << 2)
/* SDIO/mailbox ACS flag definitions */
#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET (1 << 0)
#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET (1 << 1)
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK (1 << 16)
#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK (1 << 17)
/*
* CONSOLE FLAGS
......
......@@ -137,6 +137,13 @@ static int ath10k_tm_cmd_get_version(struct ath10k *ar, struct nlattr *tb[])
return ret;
}
ret = nla_put_u32(skb, ATH10K_TM_ATTR_WMI_OP_VERSION,
ar->normal_mode_fw.fw_file.wmi_op_version);
if (ret) {
kfree_skb(skb);
return ret;
}
return cfg80211_testmode_reply(skb);
}
......
......@@ -33,6 +33,7 @@ enum ath10k_tm_attr {
ATH10K_TM_ATTR_WMI_CMDID = 3,
ATH10K_TM_ATTR_VERSION_MAJOR = 4,
ATH10K_TM_ATTR_VERSION_MINOR = 5,
ATH10K_TM_ATTR_WMI_OP_VERSION = 6,
/* keep last */
__ATH10K_TM_ATTR_AFTER_LAST,
......
......@@ -938,7 +938,10 @@ static int open_file_eeprom(struct inode *inode, struct file *file)
}
for (i = 0; i < eesize; ++i) {
AR5K_EEPROM_READ(i, val);
if (!ath5k_hw_nvram_read(ah, i, &val)) {
ret = -EIO;
goto freebuf;
}
buf[i] = val;
}
......
......@@ -399,15 +399,10 @@ int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev)
csum_dest = skb->csum_offset + csum_start;
}
if (skb_headroom(skb) < dev->needed_headroom) {
struct sk_buff *tmp_skb = skb;
skb = skb_realloc_headroom(skb, dev->needed_headroom);
kfree_skb(tmp_skb);
if (skb == NULL) {
dev->stats.tx_dropped++;
return 0;
}
if (skb_cow_head(skb, dev->needed_headroom)) {
dev->stats.tx_dropped++;
kfree_skb(skb);
return 0;
}
if (ath6kl_wmi_dix_2_dot3(ar->wmi, skb)) {
......
......@@ -369,7 +369,7 @@ void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
{
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
if (reg->power_limit != new_txpow)
if (ah->curchan && reg->power_limit != new_txpow)
ath9k_hw_set_txpowerlimit(ah, new_txpow, false);
/* read back in case value is clamped */
......
......@@ -143,7 +143,7 @@ bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
if (ah->eeprom_blob)
ret = ath9k_hw_nvram_read_firmware(ah->eeprom_blob, off, data);
else if (pdata && !pdata->use_eeprom && pdata->eeprom_data)
else if (pdata && !pdata->use_eeprom)
ret = ath9k_hw_nvram_read_pdata(pdata, off, data);
else
ret = common->bus_ops->eeprom_read(common, off, data);
......
......@@ -153,7 +153,7 @@ static int ath9k_tx99_init(struct ath_softc *sc)
sc->tx99_power,
sc->tx99_power / 2);
/* We leave the harware awake as it will be chugging on */
/* We leave the hardware awake as it will be chugging on */
return 0;
}
......
......@@ -795,15 +795,11 @@ static ssize_t wil_write_file_txmgmt(struct file *file, const char __user *buf,
struct wireless_dev *wdev = wil_to_wdev(wil);
struct cfg80211_mgmt_tx_params params;
int rc;
void *frame = kmalloc(len, GFP_KERNEL);
void *frame;
if (!frame)
return -ENOMEM;
if (copy_from_user(frame, buf, len)) {
kfree(frame);
return -EIO;
}
frame = memdup_user(buf, len);
if (IS_ERR(frame))
return PTR_ERR(frame);
params.buf = frame;
params.len = len;
......
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