Commit fb96b9c8 authored by Russell King's avatar Russell King

Merge flint.arm.linux.org.uk:/usr/src/linux-bk-2.5/linux-2.5

into flint.arm.linux.org.uk:/usr/src/linux-bk-2.5/linux-2.5-rmk
parents 2b009dcf 19e8394c
......@@ -54,7 +54,7 @@ struct safe_buffer {
dma_addr_t safe_dma_addr;
};
LIST_HEAD(safe_buffers);
static LIST_HEAD(safe_buffers);
#define SIZE_SMALL 1024
......
This diff is collapsed.
......@@ -69,9 +69,9 @@ static struct irqchip bad_chip = {
};
static struct irqdesc bad_irq_desc = {
.chip = &bad_chip,
.handle = do_bad_IRQ,
.depth = 1,
.chip = &bad_chip,
.handle = do_bad_IRQ,
.disable_depth = 1,
};
/**
......
......@@ -52,9 +52,14 @@ static const char *handler[]= { "prefetch abort", "data abort", "address excepti
void dump_backtrace_entry(unsigned long where, unsigned long from)
{
#ifdef CONFIG_KALLSYMS
printk("[<%08lx>] ", where);
print_symbol("(%s) ", where);
printk("from [<%08lx>] ", from);
print_symbol("(%s)\n", from);
#else
printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
print_symbol(" %s", where);
printk("\n");
#endif
}
/*
......@@ -503,11 +508,11 @@ baddataabort(int code, unsigned long instr, struct pt_regs *regs)
die_if_kernel("unknown data abort code", regs, instr);
}
void __bug(const char *file, int line, void *data)
volatile void __bug(const char *file, int line, void *data)
{
printk(KERN_CRIT"kernel BUG at %s:%d!", file, line);
if (data)
printk(KERN_CRIT" - extra data = %p", data);
printk(" - extra data = %p", data);
printk("\n");
*(int *)0 = 0;
}
......
......@@ -19,6 +19,9 @@
*/
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/stddef.h>
#include <linux/timer.h>
#include <linux/list.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/irq.h>
......
......@@ -360,6 +360,8 @@ int iop310_setup(int nr, struct pci_sys_data *sys)
if (!res)
panic("PCI: unable to alloc resources");
memset(res, 0, sizeof(struct resource) * 2);
switch (nr) {
case 0:
res[0].start = IOP310_PCIPRI_LOWER_IO + 0x6e000000;
......
......@@ -15,9 +15,9 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/serial_sa1100.h>
#include <asm/hardware/sa1111.h>
#include "generic.h"
#include "sa1111.h"
static void xp860_power_off(void)
......
......@@ -83,7 +83,7 @@ static void vm_region_dump(struct vm_region *head, char *fn)
struct vm_region *c;
printk("Consistent Allocation Map (%s):\n", fn);
list_for_each_entry(c, &head->list, vm_list) {
list_for_each_entry(c, &head->vm_list, vm_list) {
printk(" %p: %08lx - %08lx (0x%08x)\n", c,
c->vm_start, c->vm_end, c->vm_end - c->vm_start);
}
......
......@@ -678,7 +678,7 @@ __xscale_setup:
mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
mrc p15, 0, r0, c1, c0, 0 @ get control register
bic r0, r0, #0x0200 @ .... ..R. .... ....
bic r0, r0, #0x0082 @ .... .... B... ..A.
bic r0, r0, #0x0002 @ .... .... .... ..A.
orr r0, r0, #0x0005 @ .... .... .... .C.M
orr r0, r0, #0x3900 @ ..VI Z..S .... ....
mov pc, lr
......
......@@ -24,8 +24,8 @@
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0xfe810000, IRQ_UART2, STD_COM_FLAGS }, /* ttyS0 */ \
{ 0, BASE_BAUD, 0xfe800000, IRQ_UART1, STD_COM_FLAGS } /* ttyS1 */
{ 0, BASE_BAUD, IQ80310_UART2, IRQ_UART2, STD_COM_FLAGS }, /* ttyS0 */ \
{ 0, BASE_BAUD, IQ80310_UART1, IRQ_UART1, STD_COM_FLAGS } /* ttyS1 */
#endif // CONFIG_ARCH_IQ80310
......
......@@ -23,7 +23,7 @@
#define KERNEL_STACK_SIZE PAGE_SIZE
#define INIT_EXTRA_THREAD_INFO \
.cpu_domain = domain_val(DOMAIN_USER, DOMAIN_CLIENT) | \
.cpu_domain = domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
domain_val(DOMAIN_IO, DOMAIN_CLIENT)
......
......@@ -14,9 +14,14 @@
#define set_cr(x) \
__asm__ __volatile__( \
"mcr p15, 0, %0, c1, c0 @ set CR" \
"mcr p15, 0, %0, c1, c0, 0 @ set CR" \
: : "r" (x))
#define get_cr(x) \
__asm__ __volatile__( \
"mrc p15, 0, %0, c1, c0, 0 @ get CR" \
: "=r" (x))
#define CR_M (1 << 0) /* MMU enable */
#define CR_A (1 << 1) /* Alignment abort enable */
#define CR_C (1 << 2) /* Dcache enable */
......@@ -24,9 +29,9 @@
#define CR_P (1 << 4) /* 32-bit exception handler */
#define CR_D (1 << 5) /* 32-bit data address range */
#define CR_L (1 << 6) /* Implementation defined */
#define CD_B (1 << 7) /* Big endian */
#define CR_B (1 << 7) /* Big endian */
#define CR_S (1 << 8) /* System MMU protection */
#define CD_R (1 << 9) /* ROM MMU protection */
#define CR_R (1 << 9) /* ROM MMU protection */
#define CR_F (1 << 10) /* Implementation defined */
#define CR_Z (1 << 11) /* Implementation defined */
#define CR_I (1 << 12) /* Icache enable */
......
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