Commit fbbd8cce authored by Dmitry Baryshkov's avatar Dmitry Baryshkov

drm/msm/dpu: move UBWC/memory configuration to separate struct

UBWC and highest bank settings differ slightly between different DPU
units of the same generation, while the dpu_caps and dpu_mdp_cfg are
much more stable. To ease configuration reuse move ubwc_swizzle and
highest_bank_bit data to separate structure.
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530820/
Link: https://lore.kernel.org/r/20230404130622.509628-7-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent ac1c5ed6
...@@ -400,7 +400,6 @@ struct dpu_rotation_cfg { ...@@ -400,7 +400,6 @@ struct dpu_rotation_cfg {
* @max_mixer_blendstages max layer mixer blend stages or * @max_mixer_blendstages max layer mixer blend stages or
* supported z order * supported z order
* @qseed_type qseed2 or qseed3 support. * @qseed_type qseed2 or qseed3 support.
* @ubwc_version UBWC feature version (0x0 for not supported)
* @has_src_split source split feature status * @has_src_split source split feature status
* @has_dim_layer dim layer feature status * @has_dim_layer dim layer feature status
* @has_idle_pc indicate if idle power collapse feature is supported * @has_idle_pc indicate if idle power collapse feature is supported
...@@ -414,7 +413,6 @@ struct dpu_caps { ...@@ -414,7 +413,6 @@ struct dpu_caps {
u32 max_mixer_width; u32 max_mixer_width;
u32 max_mixer_blendstages; u32 max_mixer_blendstages;
u32 qseed_type; u32 qseed_type;
u32 ubwc_version;
bool has_src_split; bool has_src_split;
bool has_dim_layer; bool has_dim_layer;
bool has_idle_pc; bool has_idle_pc;
...@@ -543,15 +541,24 @@ struct dpu_clk_ctrl_reg { ...@@ -543,15 +541,24 @@ struct dpu_clk_ctrl_reg {
* @id: index identifying this block * @id: index identifying this block
* @base: register base offset to mdss * @base: register base offset to mdss
* @features bit mask identifying sub-blocks/features * @features bit mask identifying sub-blocks/features
* @highest_bank_bit: UBWC parameter
* @ubwc_swizzle: ubwc default swizzle setting
* @clk_ctrls clock control register definition * @clk_ctrls clock control register definition
*/ */
struct dpu_mdp_cfg { struct dpu_mdp_cfg {
DPU_HW_BLK_INFO; DPU_HW_BLK_INFO;
struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
};
/**
* struct dpu_ubwc_cfg - UBWC and memory configuration
*
* @ubwc_version UBWC feature version (0x0 for not supported)
* @highest_bank_bit: UBWC parameter
* @ubwc_swizzle: ubwc default swizzle setting
*/
struct dpu_ubwc_cfg {
u32 ubwc_version;
u32 highest_bank_bit; u32 highest_bank_bit;
u32 ubwc_swizzle; u32 ubwc_swizzle;
struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
}; };
/* struct dpu_ctl_cfg : MDP CTL instance info /* struct dpu_ctl_cfg : MDP CTL instance info
...@@ -853,6 +860,8 @@ struct dpu_perf_cfg { ...@@ -853,6 +860,8 @@ struct dpu_perf_cfg {
struct dpu_mdss_cfg { struct dpu_mdss_cfg {
const struct dpu_caps *caps; const struct dpu_caps *caps;
const struct dpu_ubwc_cfg *ubwc;
u32 mdp_count; u32 mdp_count;
const struct dpu_mdp_cfg *mdp; const struct dpu_mdp_cfg *mdp;
......
...@@ -307,25 +307,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, ...@@ -307,25 +307,25 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
DPU_FETCH_CONFIG_RESET_VALUE | DPU_FETCH_CONFIG_RESET_VALUE |
ctx->mdp->highest_bank_bit << 18); ctx->ubwc->highest_bank_bit << 18);
switch (ctx->catalog->caps->ubwc_version) { switch (ctx->ubwc->ubwc_version) {
case DPU_HW_UBWC_VER_10: case DPU_HW_UBWC_VER_10:
fast_clear = fmt->alpha_enable ? BIT(31) : 0; fast_clear = fmt->alpha_enable ? BIT(31) : 0;
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
fast_clear | (ctx->mdp->ubwc_swizzle & 0x1) | fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
BIT(8) | BIT(8) |
(ctx->mdp->highest_bank_bit << 4)); (ctx->ubwc->highest_bank_bit << 4));
break; break;
case DPU_HW_UBWC_VER_20: case DPU_HW_UBWC_VER_20:
fast_clear = fmt->alpha_enable ? BIT(31) : 0; fast_clear = fmt->alpha_enable ? BIT(31) : 0;
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
fast_clear | (ctx->mdp->ubwc_swizzle) | fast_clear | (ctx->ubwc->ubwc_swizzle) |
(ctx->mdp->highest_bank_bit << 4)); (ctx->ubwc->highest_bank_bit << 4));
break; break;
case DPU_HW_UBWC_VER_30: case DPU_HW_UBWC_VER_30:
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
BIT(30) | (ctx->mdp->ubwc_swizzle) | BIT(30) | (ctx->ubwc->ubwc_swizzle) |
(ctx->mdp->highest_bank_bit << 4)); (ctx->ubwc->highest_bank_bit << 4));
break; break;
case DPU_HW_UBWC_VER_40: case DPU_HW_UBWC_VER_40:
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
...@@ -813,7 +813,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx, ...@@ -813,7 +813,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(enum dpu_sspp idx,
/* Assign ops */ /* Assign ops */
hw_pipe->catalog = catalog; hw_pipe->catalog = catalog;
hw_pipe->mdp = &catalog->mdp[0]; hw_pipe->ubwc = catalog->ubwc;
hw_pipe->idx = idx; hw_pipe->idx = idx;
hw_pipe->cap = cfg; hw_pipe->cap = cfg;
_setup_layer_ops(hw_pipe, hw_pipe->cap->features); _setup_layer_ops(hw_pipe, hw_pipe->cap->features);
......
...@@ -342,7 +342,7 @@ struct dpu_hw_sspp_ops { ...@@ -342,7 +342,7 @@ struct dpu_hw_sspp_ops {
* @base: hardware block base structure * @base: hardware block base structure
* @hw: block hardware details * @hw: block hardware details
* @catalog: back pointer to catalog * @catalog: back pointer to catalog
* @mdp: pointer to associated mdp portion of the catalog * @ubwc: ubwc configuration data
* @idx: pipe index * @idx: pipe index
* @cap: pointer to layer_cfg * @cap: pointer to layer_cfg
* @ops: pointer to operations possible for this pipe * @ops: pointer to operations possible for this pipe
...@@ -351,7 +351,7 @@ struct dpu_hw_sspp { ...@@ -351,7 +351,7 @@ struct dpu_hw_sspp {
struct dpu_hw_blk base; struct dpu_hw_blk base;
struct dpu_hw_blk_reg_map hw; struct dpu_hw_blk_reg_map hw;
const struct dpu_mdss_cfg *catalog; const struct dpu_mdss_cfg *catalog;
const struct dpu_mdp_cfg *mdp; const struct dpu_ubwc_cfg *ubwc;
/* Pipe */ /* Pipe */
enum dpu_sspp idx; enum dpu_sspp idx;
......
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