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Kirill Smelkov
linux
Commits
fcb59bdf
Commit
fcb59bdf
authored
Dec 10, 2015
by
Linus Walleij
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Merge branch 'bcm-nsp' into devel
parents
e43d2b75
8bfcbbbc
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Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt
Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt
+80
-0
drivers/pinctrl/bcm/Kconfig
drivers/pinctrl/bcm/Kconfig
+17
-0
drivers/pinctrl/bcm/Makefile
drivers/pinctrl/bcm/Makefile
+1
-0
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
+749
-0
No files found.
Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt
0 → 100644
View file @
fcb59bdf
Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
Required properties:
- compatible:
Must be "brcm,nsp-gpio-a"
- reg:
Should contain the register physical address and length for each of
GPIO base, IO control registers
- #gpio-cells:
Must be two. The first cell is the GPIO pin number (within the
controller's pin space) and the second cell is used for the following:
bit[0]: polarity (0 for active high and 1 for active low)
- gpio-controller:
Specifies that the node is a GPIO controller
- ngpios:
Number of gpios supported (58x25 supports 32 and 58x23 supports 24)
Optional properties:
- interrupts:
Interrupt ID
- interrupt-controller:
Specifies that the node is an interrupt controller
- gpio-ranges:
Specifies the mapping between gpio controller and pin-controllers pins.
This requires 4 fields in cells defined as -
1. Phandle of pin-controller.
2. GPIO base pin offset.
3 Pin-control base pin offset.
4. number of gpio pins which are linearly mapped from pin base.
Supported generic PINCONF properties in child nodes:
- pins:
The list of pins (within the controller's own pin space) that properties
in the node apply to. Pin names are "gpio-<pin>"
- bias-disable:
Disable pin bias
- bias-pull-up:
Enable internal pull up resistor
- bias-pull-down:
Enable internal pull down resistor
- drive-strength:
Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA)
Example:
gpioa: gpio@18000020 {
compatible = "brcm,nsp-gpio-a";
reg = <0x18000020 0x100>,
<0x1803f1c4 0x1c>;
#gpio-cells = <2>;
gpio-controller;
ngpios = <32>;
gpio-ranges = <&pinctrl 0 0 31>;
interrupt-controller;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
/* Hog a few default settings */
pinctrl-names = "default";
pinctrl-0 = <&led>;
led: led {
pins = "gpio-1";
bias-pull-up;
};
pwr: pwr {
gpio-hog;
gpios = <3 1>;
output-high;
};
};
drivers/pinctrl/bcm/Kconfig
View file @
fcb59bdf
...
...
@@ -68,3 +68,20 @@ config PINCTRL_CYGNUS_MUX
The Broadcom Cygnus IOMUX driver supports group based IOMUX
configuration, with the exception that certain individual pins
can be overrided to GPIO function
config PINCTRL_NSP_GPIO
bool "Broadcom NSP GPIO (with PINCONF) driver"
depends on OF_GPIO && (ARCH_BCM_NSP || COMPILE_TEST)
select GPIOLIB_IRQCHIP
select PINCONF
select GENERIC_PINCONF
default ARCH_BCM_NSP
help
Say yes here to enable the Broadcom NSP GPIO driver.
The Broadcom Northstar Plus SoC ChipcommonA GPIO controller is
supported by this driver.
The ChipcommonA GPIO controller support basic PINCONF functions such
as bias pull up, pull down, and drive strength configurations, when
these pins are muxed to GPIO.
drivers/pinctrl/bcm/Makefile
View file @
fcb59bdf
...
...
@@ -4,3 +4,4 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_BCM2835)
+=
pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_IPROC_GPIO)
+=
pinctrl-iproc-gpio.o
obj-$(CONFIG_PINCTRL_CYGNUS_MUX)
+=
pinctrl-cygnus-mux.o
obj-$(CONFIG_PINCTRL_NSP_GPIO)
+=
pinctrl-nsp-gpio.o
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
0 → 100644
View file @
fcb59bdf
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