Commit fce8a4ac authored by Jinzhou Su's avatar Jinzhou Su Committed by Alex Deucher

drm/amdgpu: Add gfx doorbell setting for Vangogh

Using KIQ to map GFX queues instead of MMIO for gfx async ring,
add missing doorbell range setting.

v2: fix typo
Signed-off-by: default avatarJinzhou.Su <Jinzhou.Su@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c95ec47c
...@@ -5995,17 +5995,19 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, ...@@ -5995,17 +5995,19 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
{ {
u32 tmp; u32 tmp;
tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); if (!amdgpu_async_gfx_ring) {
if (ring->use_doorbell) { tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, if (ring->use_doorbell) {
DOORBELL_OFFSET, ring->doorbell_index); tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_OFFSET, ring->doorbell_index);
DOORBELL_EN, 1); tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
} else { DOORBELL_EN, 1);
tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, } else {
DOORBELL_EN, 0); tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
DOORBELL_EN, 0);
}
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
} }
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
...@@ -6349,6 +6351,8 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) ...@@ -6349,6 +6351,8 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
DOORBELL_EN, 0); DOORBELL_EN, 0);
mqd->cp_rb_doorbell_control = tmp; mqd->cp_rb_doorbell_control = tmp;
/* set doorbell range */
gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
ring->wptr = 0; ring->wptr = 0;
mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
......
...@@ -761,7 +761,7 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB ...@@ -761,7 +761,7 @@ static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TAB
return ret; return ret;
} }
int vangogh_set_default_dpm_tables(struct smu_context *smu) static int vangogh_set_default_dpm_tables(struct smu_context *smu)
{ {
struct smu_table_context *smu_table = &smu->smu_table; struct smu_table_context *smu_table = &smu->smu_table;
......
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