Commit fd1d961d authored by Dan Williams's avatar Dan Williams

x86/insn: remove pcommit

The pcommit instruction is being deprecated in favor of either ADR
(asynchronous DRAM refresh: flush-on-power-fail) at the platform level, or
posted-write-queue flush addresses as defined by the ACPI 6.x NFIT (NVDIMM
Firmware Interface Table).

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Ross Zwisler <ross.zwisler@linux.intel.com>
Acked-by: default avatarIngo Molnar <mingo@redhat.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent dfa169bb
...@@ -225,7 +225,6 @@ ...@@ -225,7 +225,6 @@
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */ #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */ #define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */ #define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */
#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */ #define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */ #define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
......
...@@ -253,52 +253,6 @@ static inline void clwb(volatile void *__p) ...@@ -253,52 +253,6 @@ static inline void clwb(volatile void *__p)
: [pax] "a" (p)); : [pax] "a" (p));
} }
/**
* pcommit_sfence() - persistent commit and fence
*
* The PCOMMIT instruction ensures that data that has been flushed from the
* processor's cache hierarchy with CLWB, CLFLUSHOPT or CLFLUSH is accepted to
* memory and is durable on the DIMM. The primary use case for this is
* persistent memory.
*
* This function shows how to properly use CLWB/CLFLUSHOPT/CLFLUSH and PCOMMIT
* with appropriate fencing.
*
* Example:
* void flush_and_commit_buffer(void *vaddr, unsigned int size)
* {
* unsigned long clflush_mask = boot_cpu_data.x86_clflush_size - 1;
* void *vend = vaddr + size;
* void *p;
*
* for (p = (void *)((unsigned long)vaddr & ~clflush_mask);
* p < vend; p += boot_cpu_data.x86_clflush_size)
* clwb(p);
*
* // SFENCE to order CLWB/CLFLUSHOPT/CLFLUSH cache flushes
* // MFENCE via mb() also works
* wmb();
*
* // PCOMMIT and the required SFENCE for ordering
* pcommit_sfence();
* }
*
* After this function completes the data pointed to by 'vaddr' has been
* accepted to memory and will be durable if the 'vaddr' points to persistent
* memory.
*
* PCOMMIT must always be ordered by an MFENCE or SFENCE, so to help simplify
* things we include both the PCOMMIT and the required SFENCE in the
* alternatives generated by pcommit_sfence().
*/
static inline void pcommit_sfence(void)
{
alternative(ASM_NOP7,
".byte 0x66, 0x0f, 0xae, 0xf8\n\t" /* pcommit */
"sfence",
X86_FEATURE_PCOMMIT);
}
#define nop() asm volatile ("nop") #define nop() asm volatile ("nop")
......
...@@ -947,7 +947,7 @@ GrpTable: Grp15 ...@@ -947,7 +947,7 @@ GrpTable: Grp15
4: XSAVE 4: XSAVE
5: XRSTOR | lfence (11B) 5: XRSTOR | lfence (11B)
6: XSAVEOPT | clwb (66) | mfence (11B) 6: XSAVEOPT | clwb (66) | mfence (11B)
7: clflush | clflushopt (66) | sfence (11B) | pcommit (66),(11B) 7: clflush | clflushopt (66) | sfence (11B)
EndTable EndTable
GrpTable: Grp16 GrpTable: Grp16
......
...@@ -947,7 +947,7 @@ GrpTable: Grp15 ...@@ -947,7 +947,7 @@ GrpTable: Grp15
4: XSAVE 4: XSAVE
5: XRSTOR | lfence (11B) 5: XRSTOR | lfence (11B)
6: XSAVEOPT | clwb (66) | mfence (11B) 6: XSAVEOPT | clwb (66) | mfence (11B)
7: clflush | clflushopt (66) | sfence (11B) | pcommit (66),(11B) 7: clflush | clflushopt (66) | sfence (11B)
EndTable EndTable
GrpTable: Grp16 GrpTable: Grp16
......
...@@ -654,5 +654,3 @@ ...@@ -654,5 +654,3 @@
"0f c7 1d 78 56 34 12 \txrstors 0x12345678",}, "0f c7 1d 78 56 34 12 \txrstors 0x12345678",},
{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", {{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "",
"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%eax,%ecx,8)",}, "0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%eax,%ecx,8)",},
{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
"66 0f ae f8 \tpcommit ",},
...@@ -764,5 +764,3 @@ ...@@ -764,5 +764,3 @@
"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%rax,%rcx,8)",}, "0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%rax,%rcx,8)",},
{{0x41, 0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", {{0x41, 0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "",
"41 0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%r8,%rcx,8)",}, "41 0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%r8,%rcx,8)",},
{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "",
"66 0f ae f8 \tpcommit ",},
...@@ -866,10 +866,6 @@ int main(void) ...@@ -866,10 +866,6 @@ int main(void)
#endif /* #ifndef __x86_64__ */ #endif /* #ifndef __x86_64__ */
/* pcommit */
asm volatile("pcommit");
/* Following line is a marker for the awk script - do not change */ /* Following line is a marker for the awk script - do not change */
asm volatile("rdtsc"); /* Stop here */ asm volatile("rdtsc"); /* Stop here */
......
...@@ -947,7 +947,7 @@ GrpTable: Grp15 ...@@ -947,7 +947,7 @@ GrpTable: Grp15
4: XSAVE 4: XSAVE
5: XRSTOR | lfence (11B) 5: XRSTOR | lfence (11B)
6: XSAVEOPT | clwb (66) | mfence (11B) 6: XSAVEOPT | clwb (66) | mfence (11B)
7: clflush | clflushopt (66) | sfence (11B) | pcommit (66),(11B) 7: clflush | clflushopt (66) | sfence (11B)
EndTable EndTable
GrpTable: Grp16 GrpTable: Grp16
......
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