Commit fd7a9d8f authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Fix g4x fbc watermark enable

'level' here means the highest level we can't use, so when checking
the fbc watermarks we need a -1 to get at the last enabled level.

While at if refactor the code a bit to declutter
g4x_compute_pipe_wm().
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200429101034.8208-12-ville.syrjala@linux.intel.comReviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
parent fc620094
...@@ -1345,6 +1345,23 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc, ...@@ -1345,6 +1345,23 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
} }
} }
static bool g4x_compute_fbc_en(const struct g4x_wm_state *wm_state,
int level)
{
if (level < G4X_WM_LEVEL_SR)
return false;
if (level >= G4X_WM_LEVEL_SR &&
wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
return false;
if (level >= G4X_WM_LEVEL_HPLL &&
wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
return false;
return true;
}
static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{ {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
...@@ -1384,7 +1401,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) ...@@ -1384,7 +1401,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
wm_state->wm.plane[plane_id] = raw->plane[plane_id]; wm_state->wm.plane[plane_id] = raw->plane[plane_id];
level = G4X_WM_LEVEL_SR; level = G4X_WM_LEVEL_SR;
if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
goto out; goto out;
...@@ -1396,7 +1412,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) ...@@ -1396,7 +1412,6 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY); wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY);
level = G4X_WM_LEVEL_HPLL; level = G4X_WM_LEVEL_HPLL;
if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) if (!g4x_raw_crtc_wm_is_valid(crtc_state, level))
goto out; goto out;
...@@ -1419,17 +1434,11 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) ...@@ -1419,17 +1434,11 @@ static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state)
/* /*
* Determine if the FBC watermark(s) can be used. IF * Determine if the FBC watermark(s) can be used. IF
* this isn't the case we prefer to disable the FBC * this isn't the case we prefer to disable the FBC
( watermark(s) rather than disable the SR/HPLL * watermark(s) rather than disable the SR/HPLL
* level(s) entirely. * level(s) entirely. 'level-1' is the highest valid
* level here.
*/ */
wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL; wm_state->fbc_en = g4x_compute_fbc_en(wm_state, level - 1);
if (level >= G4X_WM_LEVEL_SR &&
wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR))
wm_state->fbc_en = false;
else if (level >= G4X_WM_LEVEL_HPLL &&
wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL))
wm_state->fbc_en = false;
return 0; return 0;
} }
......
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