Commit fe2e27bb authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes for SPEAr from Olof Johansson:
 "These are arriving very late in the release cycle, but there has been
  a change of maintainers on the SPEAr platform and they have needed a
  while to get going.

  The patch count is higher than I would like at this point, but they're
  all relevant fixes and well-contained in their own platform code.  I
  still think it's suitable 3.5 material and I don't think it should
  increase the need for a -rc8 since they are so contained."

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: SPEAr600: Fix timer interrupt definition in spear600.dtsi
  ARM: dts: SPEAr320: Boot the board in EXTENDED_MODE
  ARM: dts: SPEAr320: Fix compatible string
  Clk: SPEAr1340: Update sys clock parent array
  clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.
  ARM: SPEAr13xx: Fix Interrupt bindings
  Clk:spear6xx:Fix: Rename clk ids within predefined limit
  Clk:spear3xx:Fix: Rename clk ids within predefined limit
  clk:spear1310:Fix: Rename clk ids within predefined limit
  clk:spear1340:Fix: Rename clk ids within predefined limit
parents a9866ba4 bae7641b
...@@ -43,8 +43,8 @@ gic: interrupt-controller@ec801000 { ...@@ -43,8 +43,8 @@ gic: interrupt-controller@ec801000 {
pmu { pmu {
compatible = "arm,cortex-a9-pmu"; compatible = "arm,cortex-a9-pmu";
interrupts = <0 8 0x04 interrupts = <0 6 0x04
0 9 0x04>; 0 7 0x04>;
}; };
L2: l2-cache { L2: l2-cache {
...@@ -119,8 +119,8 @@ fsmc: flash@b0000000 { ...@@ -119,8 +119,8 @@ fsmc: flash@b0000000 {
gmac0: eth@e2000000 { gmac0: eth@e2000000 {
compatible = "st,spear600-gmac"; compatible = "st,spear600-gmac";
reg = <0xe2000000 0x8000>; reg = <0xe2000000 0x8000>;
interrupts = <0 23 0x4 interrupts = <0 33 0x4
0 24 0x4>; 0 34 0x4>;
interrupt-names = "macirq", "eth_wake_irq"; interrupt-names = "macirq", "eth_wake_irq";
status = "disabled"; status = "disabled";
}; };
...@@ -202,6 +202,7 @@ gpio1: gpio@e0680000 { ...@@ -202,6 +202,7 @@ gpio1: gpio@e0680000 {
kbd@e0300000 { kbd@e0300000 {
compatible = "st,spear300-kbd"; compatible = "st,spear300-kbd";
reg = <0xe0300000 0x1000>; reg = <0xe0300000 0x1000>;
interrupts = <0 52 0x4>;
status = "disabled"; status = "disabled";
}; };
...@@ -224,7 +225,7 @@ rtc@e0580000 { ...@@ -224,7 +225,7 @@ rtc@e0580000 {
serial@e0000000 { serial@e0000000 {
compatible = "arm,pl011", "arm,primecell"; compatible = "arm,pl011", "arm,primecell";
reg = <0xe0000000 0x1000>; reg = <0xe0000000 0x1000>;
interrupts = <0 36 0x4>; interrupts = <0 35 0x4>;
status = "disabled"; status = "disabled";
}; };
......
...@@ -15,8 +15,8 @@ ...@@ -15,8 +15,8 @@
/include/ "spear320.dtsi" /include/ "spear320.dtsi"
/ { / {
model = "ST SPEAr300 Evaluation Board"; model = "ST SPEAr320 Evaluation Board";
compatible = "st,spear300-evb", "st,spear300"; compatible = "st,spear320-evb", "st,spear320";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -26,7 +26,7 @@ memory { ...@@ -26,7 +26,7 @@ memory {
ahb { ahb {
pinmux@b3000000 { pinmux@b3000000 {
st,pinmux-mode = <3>; st,pinmux-mode = <4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&state_default>; pinctrl-0 = <&state_default>;
......
...@@ -181,6 +181,7 @@ i2c@d0200000 { ...@@ -181,6 +181,7 @@ i2c@d0200000 {
timer@f0000000 { timer@f0000000 {
compatible = "st,spear-timer"; compatible = "st,spear-timer";
reg = <0xf0000000 0x400>; reg = <0xf0000000 0x400>;
interrupt-parent = <&vic0>;
interrupts = <16>; interrupts = <16>;
}; };
}; };
......
...@@ -87,7 +87,7 @@ void __init spear3xx_map_io(void) ...@@ -87,7 +87,7 @@ void __init spear3xx_map_io(void)
static void __init spear3xx_timer_init(void) static void __init spear3xx_timer_init(void)
{ {
char pclk_name[] = "pll3_48m_clk"; char pclk_name[] = "pll3_clk";
struct clk *gpt_clk, *pclk; struct clk *gpt_clk, *pclk;
spear3xx_clk_init(); spear3xx_clk_init();
......
...@@ -423,7 +423,7 @@ void __init spear6xx_map_io(void) ...@@ -423,7 +423,7 @@ void __init spear6xx_map_io(void)
static void __init spear6xx_timer_init(void) static void __init spear6xx_timer_init(void)
{ {
char pclk_name[] = "pll3_48m_clk"; char pclk_name[] = "pll3_clk";
struct clk *gpt_clk, *pclk; struct clk *gpt_clk, *pclk;
spear6xx_clk_init(); spear6xx_clk_init();
......
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...@@ -97,13 +97,12 @@ static struct aux_rate_tbl aux_rtbl[] = { ...@@ -97,13 +97,12 @@ static struct aux_rate_tbl aux_rtbl[] = {
{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
}; };
static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", }; static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk", static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
}; static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", }; static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", }; static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", }; static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", };
static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
"pll2_clk", }; "pll2_clk", };
...@@ -136,9 +135,9 @@ void __init spear6xx_clk_init(void) ...@@ -136,9 +135,9 @@ void __init spear6xx_clk_init(void)
clk_register_clkdev(clk, NULL, "rtc-spear"); clk_register_clkdev(clk, NULL, "rtc-spear");
/* clock derived from 30 MHz osc clk */ /* clock derived from 30 MHz osc clk */
clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0, clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
48000000); 48000000);
clk_register_clkdev(clk, "pll3_48m_clk", NULL); clk_register_clkdev(clk, "pll3_clk", NULL);
clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
...@@ -146,9 +145,9 @@ void __init spear6xx_clk_init(void) ...@@ -146,9 +145,9 @@ void __init spear6xx_clk_init(void)
clk_register_clkdev(clk, "vco1_clk", NULL); clk_register_clkdev(clk, "vco1_clk", NULL);
clk_register_clkdev(clk1, "pll1_clk", NULL); clk_register_clkdev(clk1, "pll1_clk", NULL);
clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
"osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); &_lock, &clk1, NULL);
clk_register_clkdev(clk, "vco2_clk", NULL); clk_register_clkdev(clk, "vco2_clk", NULL);
clk_register_clkdev(clk1, "pll2_clk", NULL); clk_register_clkdev(clk1, "pll2_clk", NULL);
...@@ -165,111 +164,111 @@ void __init spear6xx_clk_init(void) ...@@ -165,111 +164,111 @@ void __init spear6xx_clk_init(void)
HCLK_RATIO_MASK, 0, &_lock); HCLK_RATIO_MASK, 0, &_lock);
clk_register_clkdev(clk, "ahb_clk", NULL); clk_register_clkdev(clk, "ahb_clk", NULL);
clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
"pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
ARRAY_SIZE(aux_rtbl), &_lock, &clk1); &_lock, &clk1);
clk_register_clkdev(clk, "uart_synth_clk", NULL); clk_register_clkdev(clk, "uart_syn_clk", NULL);
clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents, clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG,
UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "uart_mux_clk", NULL); clk_register_clkdev(clk, "uart_mclk", NULL);
clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0, clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock); UART0_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "d0000000.serial"); clk_register_clkdev(clk, NULL, "d0000000.serial");
clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0, clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock); UART1_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "d0080000.serial"); clk_register_clkdev(clk, NULL, "d0080000.serial");
clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk", clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
"pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
ARRAY_SIZE(aux_rtbl), &_lock, &clk1); &_lock, &clk1);
clk_register_clkdev(clk, "firda_synth_clk", NULL); clk_register_clkdev(clk, "firda_syn_clk", NULL);
clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL); clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents, clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG,
FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "firda_mux_clk", NULL); clk_register_clkdev(clk, "firda_mclk", NULL);
clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0, clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "firda"); clk_register_clkdev(clk, NULL, "firda");
clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk", clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
"pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl, 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
ARRAY_SIZE(aux_rtbl), &_lock, &clk1); &_lock, &clk1);
clk_register_clkdev(clk, "clcd_synth_clk", NULL); clk_register_clkdev(clk, "clcd_syn_clk", NULL);
clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL); clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents, clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG,
CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "clcd_mux_clk", NULL); clk_register_clkdev(clk, "clcd_mclk", NULL);
clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0, clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "clcd"); clk_register_clkdev(clk, NULL, "clcd");
/* gpt clocks */ /* gpt clocks */
clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG, clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL); clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents, clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, NULL, "gpt0"); clk_register_clkdev(clk, NULL, "gpt0");
clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents, clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG,
GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gpt1_mux_clk", NULL); clk_register_clkdev(clk, "gpt1_mclk", NULL);
clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "gpt1"); clk_register_clkdev(clk, NULL, "gpt1");
clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG, clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
clk_register_clkdev(clk, "gpt2_synth_clk", NULL); clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents, clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG,
GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gpt2_mux_clk", NULL); clk_register_clkdev(clk, "gpt2_mclk", NULL);
clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "gpt2"); clk_register_clkdev(clk, NULL, "gpt2");
clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG, clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
clk_register_clkdev(clk, "gpt3_synth_clk", NULL); clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents, clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG,
GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
clk_register_clkdev(clk, "gpt3_mux_clk", NULL); clk_register_clkdev(clk, "gpt3_mclk", NULL);
clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0, clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "gpt3"); clk_register_clkdev(clk, NULL, "gpt3");
/* clock derived from pll3 clk */ /* clock derived from pll3 clk */
clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0, clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "usbh.0_clk"); clk_register_clkdev(clk, NULL, "usbh.0_clk");
clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0, clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "usbh.1_clk"); clk_register_clkdev(clk, NULL, "usbh.1_clk");
clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0, clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); USBD_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "designware_udc"); clk_register_clkdev(clk, NULL, "designware_udc");
/* clock derived from ahb clk */ /* clock derived from ahb clk */
...@@ -278,9 +277,8 @@ void __init spear6xx_clk_init(void) ...@@ -278,9 +277,8 @@ void __init spear6xx_clk_init(void)
clk_register_clkdev(clk, "ahbmult2_clk", NULL); clk_register_clkdev(clk, "ahbmult2_clk", NULL);
clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
ARRAY_SIZE(ddr_parents), ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT,
0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, MCTR_CLK_MASK, 0, &_lock);
&_lock);
clk_register_clkdev(clk, "ddr_clk", NULL); clk_register_clkdev(clk, "ddr_clk", NULL);
clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
......
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