Commit fee10bd2 authored by Naga Sureshkumar Relli's avatar Naga Sureshkumar Relli Committed by Michal Simek

memory: pl353: Add driver for arm pl353 static memory controller

Add driver for arm pl353 static memory controller. This controller is used in
Xilinx Zynq SoC for interfacing the NAND and NOR/SRAM memory devices.
Signed-off-by: default avatarNaga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent b0b41af1
...@@ -145,6 +145,15 @@ config DA8XX_DDRCTL ...@@ -145,6 +145,15 @@ config DA8XX_DDRCTL
Texas Instruments da8xx SoCs. It's used to tweak various memory Texas Instruments da8xx SoCs. It's used to tweak various memory
controller configuration options. controller configuration options.
config PL353_SMC
tristate "ARM PL35X Static Memory Controller(SMC) driver"
default y
depends on ARM
depends on ARM_AMBA
help
This driver is for the ARM PL351/PL353 Static Memory
Controller(SMC) module.
source "drivers/memory/samsung/Kconfig" source "drivers/memory/samsung/Kconfig"
source "drivers/memory/tegra/Kconfig" source "drivers/memory/tegra/Kconfig"
......
...@@ -19,6 +19,7 @@ obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o ...@@ -19,6 +19,7 @@ obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o
obj-$(CONFIG_MTK_SMI) += mtk-smi.o obj-$(CONFIG_MTK_SMI) += mtk-smi.o
obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
obj-$(CONFIG_PL353_SMC) += pl353-smc.o
obj-$(CONFIG_SAMSUNG_MC) += samsung/ obj-$(CONFIG_SAMSUNG_MC) += samsung/
obj-$(CONFIG_TEGRA_MC) += tegra/ obj-$(CONFIG_TEGRA_MC) += tegra/
......
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
/*
* ARM PL353 SMC Driver Header
*
* Copyright (C) 2012 - 2018 Xilinx, Inc
*/
#ifndef __LINUX_PL353_SMC_H
#define __LINUX_PL353_SMC_H
enum pl353_smc_ecc_mode {
PL353_SMC_ECCMODE_BYPASS = 0,
PL353_SMC_ECCMODE_APB = 1,
PL353_SMC_ECCMODE_MEM = 2
};
enum pl353_smc_mem_width {
PL353_SMC_MEM_WIDTH_8 = 0,
PL353_SMC_MEM_WIDTH_16 = 1
};
u32 pl353_smc_get_ecc_val(int ecc_reg);
bool pl353_smc_ecc_is_busy(void);
int pl353_smc_get_nand_int_status_raw(void);
void pl353_smc_clr_nand_int(void);
int pl353_smc_set_ecc_mode(enum pl353_smc_ecc_mode mode);
int pl353_smc_set_ecc_pg_size(unsigned int pg_sz);
int pl353_smc_set_buswidth(unsigned int bw);
void pl353_smc_set_cycles(u32 timings[]);
#endif
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