Commit feeb7201 authored by Bjorn Helgaas's avatar Bjorn Helgaas

PCI: dra7xx: Use generic DesignWare accessors

The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the dra7xx
driver.  No functional change intended.
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 03fa2ae1
...@@ -83,17 +83,6 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset, ...@@ -83,17 +83,6 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
writel(value, pcie->base + offset); writel(value, pcie->base + offset);
} }
static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
{
return readl(pp->dbi_base + offset);
}
static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
u32 value)
{
writel(value, pp->dbi_base + offset);
}
static int dra7xx_pcie_link_up(struct pcie_port *pp) static int dra7xx_pcie_link_up(struct pcie_port *pp)
{ {
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp); struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
...@@ -448,9 +437,9 @@ static int dra7xx_pcie_suspend(struct device *dev) ...@@ -448,9 +437,9 @@ static int dra7xx_pcie_suspend(struct device *dev)
u32 val; u32 val;
/* clear MSE */ /* clear MSE */
val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND); val = dw_pcie_readl_rc(pp, PCI_COMMAND);
val &= ~PCI_COMMAND_MEMORY; val &= ~PCI_COMMAND_MEMORY;
dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val); dw_pcie_writel_rc(pp, PCI_COMMAND, val);
return 0; return 0;
} }
...@@ -462,9 +451,9 @@ static int dra7xx_pcie_resume(struct device *dev) ...@@ -462,9 +451,9 @@ static int dra7xx_pcie_resume(struct device *dev)
u32 val; u32 val;
/* set MSE */ /* set MSE */
val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND); val = dw_pcie_readl_rc(pp, PCI_COMMAND);
val |= PCI_COMMAND_MEMORY; val |= PCI_COMMAND_MEMORY;
dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val); dw_pcie_writel_rc(pp, PCI_COMMAND, val);
return 0; return 0;
} }
......
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