Commit ff83fec8 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'drm-fixes-2023-01-20' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Just a pretty regular week for this stage of things, amdgpu and i915,
  along with some msm and misc others.

  fb-helper:
   - switcheroo fix

  msm:
   - kexec shutdown fix
   - fix potential double free

  i915:
   - Reject display plane with height == 0
   - re-disable RC6p on Sandy Bridge
   - Fix hugepages' selftest
   - DG2 hw workarounds
   - switcheroo fix

  vc4:
   - fix a memory leak

  panfrost:
   - Kconfig fix

  amdgpu:
   - Fix display scaling
   - Fix RN/CZN power reporting on some firmware versions
   - Colorspace fixes
   - Fix resource freeing in error case in CS IOCTL
   - Fix warning on driver unload
   - GC11 fixes
   - DCN 3.1.4/5 S/G display workarounds"

* tag 'drm-fixes-2023-01-20' of git://anongit.freedesktop.org/drm/drm: (24 commits)
  drm/amd/display: disable S/G display on DCN 3.1.4
  drm/amd/display: disable S/G display on DCN 3.1.5
  drm/amdgpu: allow multipipe policy on ASICs with one MEC
  drm/amdgpu: correct MEC number for gfx11 APUs
  drm/amd/display: fix issues with driver unload
  drm/amdgpu: fix amdgpu_job_free_resources v2
  drm/amd/display: Fix COLOR_SPACE_YCBCR2020_TYPE matrix
  drm/amd/display: Calculate output_color_space after pixel encoding adjustment
  drm/amdgpu: fix cleaning up reserved VMID on release
  drm/amdgpu: Correct the power calcultion for Renior/Cezanne.
  drm/amd/display: Fix set scaling doesn's work
  drm/i915: Remove unused variable
  drm/i915/dg2: Introduce Wa_18019271663
  drm/i915/dg2: Introduce Wa_18018764978
  drm/fb-helper: Set framebuffer for vga-switcheroo clients
  drm/i915: Allow switching away via vga-switcheroo if uninitialized
  drm/i915/selftests: Unwind hugepages to drop wakeref on error
  drm/i915: re-disable RC6p on Sandy Bridge
  drm/panfrost: fix GENERIC_ATOMIC64 dependency
  drm/i915/display: Check source height is > 0
  ...
parents 35929dae 3f30a6e6
...@@ -156,6 +156,9 @@ static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev) ...@@ -156,6 +156,9 @@ static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev)
return amdgpu_compute_multipipe == 1; return amdgpu_compute_multipipe == 1;
} }
if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0))
return true;
/* FIXME: spreading the queues across pipes causes perf regressions /* FIXME: spreading the queues across pipes causes perf regressions
* on POLARIS11 compute workloads */ * on POLARIS11 compute workloads */
if (adev->asic_type == CHIP_POLARIS11) if (adev->asic_type == CHIP_POLARIS11)
......
...@@ -497,6 +497,7 @@ void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, ...@@ -497,6 +497,7 @@ void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
!--id_mgr->reserved_use_count) { !--id_mgr->reserved_use_count) {
/* give the reserved ID back to normal round robin */ /* give the reserved ID back to normal round robin */
list_add(&id_mgr->reserved->list, &id_mgr->ids_lru); list_add(&id_mgr->reserved->list, &id_mgr->ids_lru);
id_mgr->reserved = NULL;
} }
vm->reserved_vmid[vmhub] = false; vm->reserved_vmid[vmhub] = false;
mutex_unlock(&id_mgr->lock); mutex_unlock(&id_mgr->lock);
......
...@@ -161,8 +161,14 @@ void amdgpu_job_free_resources(struct amdgpu_job *job) ...@@ -161,8 +161,14 @@ void amdgpu_job_free_resources(struct amdgpu_job *job)
struct dma_fence *f; struct dma_fence *f;
unsigned i; unsigned i;
/* use sched fence if available */ /* Check if any fences where initialized */
f = job->base.s_fence ? &job->base.s_fence->finished : &job->hw_fence; if (job->base.s_fence && job->base.s_fence->finished.ops)
f = &job->base.s_fence->finished;
else if (job->hw_fence.ops)
f = &job->hw_fence;
else
f = NULL;
for (i = 0; i < job->num_ibs; ++i) for (i = 0; i < job->num_ibs; ++i)
amdgpu_ib_free(ring->adev, &job->ibs[i], f); amdgpu_ib_free(ring->adev, &job->ibs[i], f);
} }
......
...@@ -1287,10 +1287,8 @@ static int gfx_v11_0_sw_init(void *handle) ...@@ -1287,10 +1287,8 @@ static int gfx_v11_0_sw_init(void *handle)
switch (adev->ip_versions[GC_HWIP][0]) { switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 2): case IP_VERSION(11, 0, 2):
case IP_VERSION(11, 0, 3): case IP_VERSION(11, 0, 3):
case IP_VERSION(11, 0, 4):
adev->gfx.me.num_me = 1; adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1; adev->gfx.me.num_queue_per_pipe = 1;
...@@ -1298,6 +1296,15 @@ static int gfx_v11_0_sw_init(void *handle) ...@@ -1298,6 +1296,15 @@ static int gfx_v11_0_sw_init(void *handle)
adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 4; adev->gfx.mec.num_queue_per_pipe = 4;
break; break;
case IP_VERSION(11, 0, 1):
case IP_VERSION(11, 0, 4):
adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1;
adev->gfx.me.num_queue_per_pipe = 1;
adev->gfx.mec.num_mec = 1;
adev->gfx.mec.num_pipe_per_mec = 4;
adev->gfx.mec.num_queue_per_pipe = 4;
break;
default: default:
adev->gfx.me.num_me = 1; adev->gfx.me.num_me = 1;
adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_pipe_per_me = 1;
......
...@@ -1503,8 +1503,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) ...@@ -1503,8 +1503,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
case IP_VERSION(3, 0, 1): case IP_VERSION(3, 0, 1):
case IP_VERSION(3, 1, 2): case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 1, 3): case IP_VERSION(3, 1, 3):
case IP_VERSION(3, 1, 4):
case IP_VERSION(3, 1, 5):
case IP_VERSION(3, 1, 6): case IP_VERSION(3, 1, 6):
init_data.flags.gpu_vm_support = true; init_data.flags.gpu_vm_support = true;
break; break;
...@@ -1730,10 +1728,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) ...@@ -1730,10 +1728,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
adev->dm.vblank_control_workqueue = NULL; adev->dm.vblank_control_workqueue = NULL;
} }
for (i = 0; i < adev->dm.display_indexes_num; i++) {
drm_encoder_cleanup(&adev->dm.mst_encoders[i].base);
}
amdgpu_dm_destroy_drm_device(&adev->dm); amdgpu_dm_destroy_drm_device(&adev->dm);
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
...@@ -5311,8 +5305,6 @@ static void fill_stream_properties_from_drm_display_mode( ...@@ -5311,8 +5305,6 @@ static void fill_stream_properties_from_drm_display_mode(
timing_out->aspect_ratio = get_aspect_ratio(mode_in); timing_out->aspect_ratio = get_aspect_ratio(mode_in);
stream->output_color_space = get_output_color_space(timing_out);
stream->out_transfer_func->type = TF_TYPE_PREDEFINED; stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
...@@ -5323,6 +5315,8 @@ static void fill_stream_properties_from_drm_display_mode( ...@@ -5323,6 +5315,8 @@ static void fill_stream_properties_from_drm_display_mode(
adjust_colour_depth_from_display_info(timing_out, info); adjust_colour_depth_from_display_info(timing_out, info);
} }
} }
stream->output_color_space = get_output_color_space(timing_out);
} }
static void fill_audio_info(struct audio_info *audio_info, static void fill_audio_info(struct audio_info *audio_info,
...@@ -9530,8 +9524,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, ...@@ -9530,8 +9524,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
goto fail; goto fail;
} }
if (dm_old_con_state->abm_level != if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
dm_new_con_state->abm_level) dm_old_con_state->scaling != dm_new_con_state->scaling)
new_crtc_state->connectors_changed = true; new_crtc_state->connectors_changed = true;
} }
......
...@@ -468,7 +468,6 @@ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs ...@@ -468,7 +468,6 @@ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs
static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
{ {
drm_encoder_cleanup(encoder); drm_encoder_cleanup(encoder);
kfree(encoder);
} }
static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
......
...@@ -90,8 +90,8 @@ static const struct out_csc_color_matrix_type output_csc_matrix[] = { ...@@ -90,8 +90,8 @@ static const struct out_csc_color_matrix_type output_csc_matrix[] = {
{ 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} }, 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
{ COLOR_SPACE_YCBCR2020_TYPE, { COLOR_SPACE_YCBCR2020_TYPE,
{ 0x1000, 0xF149, 0xFEB7, 0x0000, 0x0868, 0x15B2, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868, 0x15B2,
0x01E6, 0x0000, 0xFB88, 0xF478, 0x1000, 0x0000} }, 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} },
{ COLOR_SPACE_YCBCR709_BLACK_TYPE, { COLOR_SPACE_YCBCR709_BLACK_TYPE,
{ 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000, { 0x0000, 0x0000, 0x0000, 0x1000, 0x0000, 0x0000,
0x0000, 0x0200, 0x0000, 0x0000, 0x0000, 0x1000} }, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000, 0x1000} },
......
...@@ -1171,6 +1171,7 @@ static int renoir_get_smu_metrics_data(struct smu_context *smu, ...@@ -1171,6 +1171,7 @@ static int renoir_get_smu_metrics_data(struct smu_context *smu,
int ret = 0; int ret = 0;
uint32_t apu_percent = 0; uint32_t apu_percent = 0;
uint32_t dgpu_percent = 0; uint32_t dgpu_percent = 0;
struct amdgpu_device *adev = smu->adev;
ret = smu_cmn_get_metrics_table(smu, ret = smu_cmn_get_metrics_table(smu,
...@@ -1196,7 +1197,11 @@ static int renoir_get_smu_metrics_data(struct smu_context *smu, ...@@ -1196,7 +1197,11 @@ static int renoir_get_smu_metrics_data(struct smu_context *smu,
*value = metrics->AverageUvdActivity / 100; *value = metrics->AverageUvdActivity / 100;
break; break;
case METRICS_AVERAGE_SOCKETPOWER: case METRICS_AVERAGE_SOCKETPOWER:
*value = (metrics->CurrentSocketPower << 8) / 1000; if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) && (adev->pm.fw_version >= 0x40000f)) ||
((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0)) && (adev->pm.fw_version >= 0x373200)))
*value = metrics->CurrentSocketPower << 8;
else
*value = (metrics->CurrentSocketPower << 8) / 1000;
break; break;
case METRICS_TEMPERATURE_EDGE: case METRICS_TEMPERATURE_EDGE:
*value = (metrics->GfxTemperature / 100) * *value = (metrics->GfxTemperature / 100) *
......
...@@ -30,7 +30,9 @@ ...@@ -30,7 +30,9 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/console.h> #include <linux/console.h>
#include <linux/pci.h>
#include <linux/sysrq.h> #include <linux/sysrq.h>
#include <linux/vga_switcheroo.h>
#include <drm/drm_atomic.h> #include <drm/drm_atomic.h>
#include <drm/drm_drv.h> #include <drm/drm_drv.h>
...@@ -1909,6 +1911,11 @@ static int drm_fb_helper_single_fb_probe(struct drm_fb_helper *fb_helper, ...@@ -1909,6 +1911,11 @@ static int drm_fb_helper_single_fb_probe(struct drm_fb_helper *fb_helper,
return ret; return ret;
strcpy(fb_helper->fb->comm, "[fbcon]"); strcpy(fb_helper->fb->comm, "[fbcon]");
/* Set the fb info for vgaswitcheroo clients. Does nothing otherwise. */
if (dev_is_pci(dev->dev))
vga_switcheroo_client_fb_set(to_pci_dev(dev->dev), fb_helper->info);
return 0; return 0;
} }
......
...@@ -1627,7 +1627,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) ...@@ -1627,7 +1627,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
u32 offset; u32 offset;
int ret; int ret;
if (w > max_width || w < min_width || h > max_height) { if (w > max_width || w < min_width || h > max_height || h < 1) {
drm_dbg_kms(&dev_priv->drm, drm_dbg_kms(&dev_priv->drm,
"requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n", "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
w, h, min_width, max_width, max_height); w, h, min_width, max_width, max_height);
......
...@@ -1847,7 +1847,7 @@ static int igt_shrink_thp(void *arg) ...@@ -1847,7 +1847,7 @@ static int igt_shrink_thp(void *arg)
I915_SHRINK_ACTIVE); I915_SHRINK_ACTIVE);
i915_vma_unpin(vma); i915_vma_unpin(vma);
if (err) if (err)
goto out_put; goto out_wf;
/* /*
* Now that the pages are *unpinned* shrinking should invoke * Now that the pages are *unpinned* shrinking should invoke
...@@ -1863,19 +1863,19 @@ static int igt_shrink_thp(void *arg) ...@@ -1863,19 +1863,19 @@ static int igt_shrink_thp(void *arg)
pr_err("unexpected pages mismatch, should_swap=%s\n", pr_err("unexpected pages mismatch, should_swap=%s\n",
str_yes_no(should_swap)); str_yes_no(should_swap));
err = -EINVAL; err = -EINVAL;
goto out_put; goto out_wf;
} }
if (should_swap == (obj->mm.page_sizes.sg || obj->mm.page_sizes.phys)) { if (should_swap == (obj->mm.page_sizes.sg || obj->mm.page_sizes.phys)) {
pr_err("unexpected residual page-size bits, should_swap=%s\n", pr_err("unexpected residual page-size bits, should_swap=%s\n",
str_yes_no(should_swap)); str_yes_no(should_swap));
err = -EINVAL; err = -EINVAL;
goto out_put; goto out_wf;
} }
err = i915_vma_pin(vma, 0, 0, flags); err = i915_vma_pin(vma, 0, 0, flags);
if (err) if (err)
goto out_put; goto out_wf;
while (n--) { while (n--) {
err = cpu_check(obj, n, 0xdeadbeaf); err = cpu_check(obj, n, 0xdeadbeaf);
......
...@@ -429,9 +429,10 @@ ...@@ -429,9 +429,10 @@
#define RC_OP_FLUSH_ENABLE (1 << 0) #define RC_OP_FLUSH_ENABLE (1 << 0)
#define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2)
#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1 << 6) #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1 << 6) #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1 << 1) #define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6)
#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1)
#define GEN7_GT_MODE _MMIO(0x7008) #define GEN7_GT_MODE _MMIO(0x7008)
#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
...@@ -457,6 +458,9 @@ ...@@ -457,6 +458,9 @@
#define GEN8_L3CNTLREG _MMIO(0x7034) #define GEN8_L3CNTLREG _MMIO(0x7034)
#define GEN8_ERRDETBCTRL (1 << 9) #define GEN8_ERRDETBCTRL (1 << 9)
#define PSS_MODE2 _MMIO(0x703c)
#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
#define GEN7_SC_INSTDONE _MMIO(0x7100) #define GEN7_SC_INSTDONE _MMIO(0x7100)
#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
......
...@@ -771,11 +771,19 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine, ...@@ -771,11 +771,19 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_14014947963:dg2 */ /* Wa_14014947963:dg2 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) || if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915)) IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
/* Wa_18018764978:dg2 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
/* Wa_15010599737:dg2 */ /* Wa_15010599737:dg2 */
wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
/* Wa_18019271663:dg2 */
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
} }
static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine, static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
......
...@@ -1069,12 +1069,9 @@ static int i915_driver_open(struct drm_device *dev, struct drm_file *file) ...@@ -1069,12 +1069,9 @@ static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
*/ */
static void i915_driver_lastclose(struct drm_device *dev) static void i915_driver_lastclose(struct drm_device *dev)
{ {
struct drm_i915_private *i915 = to_i915(dev);
intel_fbdev_restore_mode(dev); intel_fbdev_restore_mode(dev);
if (HAS_DISPLAY(i915)) vga_switcheroo_process_delayed_switch();
vga_switcheroo_process_delayed_switch();
} }
static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
......
...@@ -423,7 +423,8 @@ static const struct intel_device_info ilk_m_info = { ...@@ -423,7 +423,8 @@ static const struct intel_device_info ilk_m_info = {
.has_coherent_ggtt = true, \ .has_coherent_ggtt = true, \
.has_llc = 1, \ .has_llc = 1, \
.has_rc6 = 1, \ .has_rc6 = 1, \
.has_rc6p = 1, \ /* snb does support rc6p, but enabling it causes various issues */ \
.has_rc6p = 0, \
.has_rps = true, \ .has_rps = true, \
.dma_mask_size = 40, \ .dma_mask_size = 40, \
.__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \ .__runtime.ppgtt_type = INTEL_PPGTT_ALIASING, \
......
...@@ -19,6 +19,10 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev, ...@@ -19,6 +19,10 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev,
dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n"); dev_err(&pdev->dev, "DRM not initialized, aborting switch.\n");
return; return;
} }
if (!HAS_DISPLAY(i915)) {
dev_err(&pdev->dev, "Device state not initialized, aborting switch.\n");
return;
}
if (state == VGA_SWITCHEROO_ON) { if (state == VGA_SWITCHEROO_ON) {
drm_info(&i915->drm, "switched on\n"); drm_info(&i915->drm, "switched on\n");
...@@ -44,7 +48,7 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev) ...@@ -44,7 +48,7 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
* locking inversion with the driver load path. And the access here is * locking inversion with the driver load path. And the access here is
* completely racy anyway. So don't bother with locking for now. * completely racy anyway. So don't bother with locking for now.
*/ */
return i915 && atomic_read(&i915->drm.open_count) == 0; return i915 && HAS_DISPLAY(i915) && atomic_read(&i915->drm.open_count) == 0;
} }
static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
......
...@@ -551,13 +551,14 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) ...@@ -551,13 +551,14 @@ static int adreno_bind(struct device *dev, struct device *master, void *data)
return 0; return 0;
} }
static int adreno_system_suspend(struct device *dev);
static void adreno_unbind(struct device *dev, struct device *master, static void adreno_unbind(struct device *dev, struct device *master,
void *data) void *data)
{ {
struct msm_drm_private *priv = dev_get_drvdata(master); struct msm_drm_private *priv = dev_get_drvdata(master);
struct msm_gpu *gpu = dev_to_gpu(dev); struct msm_gpu *gpu = dev_to_gpu(dev);
pm_runtime_force_suspend(dev); WARN_ON_ONCE(adreno_system_suspend(dev));
gpu->funcs->destroy(gpu); gpu->funcs->destroy(gpu);
priv->gpu_pdev = NULL; priv->gpu_pdev = NULL;
...@@ -609,7 +610,7 @@ static int adreno_remove(struct platform_device *pdev) ...@@ -609,7 +610,7 @@ static int adreno_remove(struct platform_device *pdev)
static void adreno_shutdown(struct platform_device *pdev) static void adreno_shutdown(struct platform_device *pdev)
{ {
pm_runtime_force_suspend(&pdev->dev); WARN_ON_ONCE(adreno_system_suspend(&pdev->dev));
} }
static const struct of_device_id dt_match[] = { static const struct of_device_id dt_match[] = {
......
...@@ -352,6 +352,8 @@ int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, ...@@ -352,6 +352,8 @@ int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
/* Ensure string is null terminated: */ /* Ensure string is null terminated: */
str[len] = '\0'; str[len] = '\0';
mutex_lock(&gpu->lock);
if (param == MSM_PARAM_COMM) { if (param == MSM_PARAM_COMM) {
paramp = &ctx->comm; paramp = &ctx->comm;
} else { } else {
...@@ -361,6 +363,8 @@ int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, ...@@ -361,6 +363,8 @@ int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
kfree(*paramp); kfree(*paramp);
*paramp = str; *paramp = str;
mutex_unlock(&gpu->lock);
return 0; return 0;
} }
case MSM_PARAM_SYSPROF: case MSM_PARAM_SYSPROF:
......
...@@ -335,6 +335,8 @@ static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char ** ...@@ -335,6 +335,8 @@ static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **
struct msm_file_private *ctx = submit->queue->ctx; struct msm_file_private *ctx = submit->queue->ctx;
struct task_struct *task; struct task_struct *task;
WARN_ON(!mutex_is_locked(&submit->gpu->lock));
/* Note that kstrdup will return NULL if argument is NULL: */ /* Note that kstrdup will return NULL if argument is NULL: */
*comm = kstrdup(ctx->comm, GFP_KERNEL); *comm = kstrdup(ctx->comm, GFP_KERNEL);
*cmd = kstrdup(ctx->cmdline, GFP_KERNEL); *cmd = kstrdup(ctx->cmdline, GFP_KERNEL);
......
...@@ -376,10 +376,18 @@ struct msm_file_private { ...@@ -376,10 +376,18 @@ struct msm_file_private {
*/ */
int sysprof; int sysprof;
/** comm: Overridden task comm, see MSM_PARAM_COMM */ /**
* comm: Overridden task comm, see MSM_PARAM_COMM
*
* Accessed under msm_gpu::lock
*/
char *comm; char *comm;
/** cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE */ /**
* cmdline: Overridden task cmdline, see MSM_PARAM_CMDLINE
*
* Accessed under msm_gpu::lock
*/
char *cmdline; char *cmdline;
/** /**
......
...@@ -3,7 +3,8 @@ ...@@ -3,7 +3,8 @@
config DRM_PANFROST config DRM_PANFROST
tristate "Panfrost (DRM support for ARM Mali Midgard/Bifrost GPUs)" tristate "Panfrost (DRM support for ARM Mali Midgard/Bifrost GPUs)"
depends on DRM depends on DRM
depends on ARM || ARM64 || (COMPILE_TEST && !GENERIC_ATOMIC64) depends on ARM || ARM64 || COMPILE_TEST
depends on !GENERIC_ATOMIC64 # for IOMMU_IO_PGTABLE_LPAE
depends on MMU depends on MMU
select DRM_SCHED select DRM_SCHED
select IOMMU_SUPPORT select IOMMU_SUPPORT
......
...@@ -179,6 +179,7 @@ static void vc4_bo_destroy(struct vc4_bo *bo) ...@@ -179,6 +179,7 @@ static void vc4_bo_destroy(struct vc4_bo *bo)
bo->validated_shader = NULL; bo->validated_shader = NULL;
} }
mutex_destroy(&bo->madv_lock);
drm_gem_dma_free(&bo->base); drm_gem_dma_free(&bo->base);
} }
...@@ -394,7 +395,6 @@ struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size) ...@@ -394,7 +395,6 @@ struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size)
{ {
struct vc4_dev *vc4 = to_vc4_dev(dev); struct vc4_dev *vc4 = to_vc4_dev(dev);
struct vc4_bo *bo; struct vc4_bo *bo;
int ret;
if (WARN_ON_ONCE(vc4->is_vc5)) if (WARN_ON_ONCE(vc4->is_vc5))
return ERR_PTR(-ENODEV); return ERR_PTR(-ENODEV);
...@@ -406,9 +406,7 @@ struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size) ...@@ -406,9 +406,7 @@ struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size)
bo->madv = VC4_MADV_WILLNEED; bo->madv = VC4_MADV_WILLNEED;
refcount_set(&bo->usecnt, 0); refcount_set(&bo->usecnt, 0);
ret = drmm_mutex_init(dev, &bo->madv_lock); mutex_init(&bo->madv_lock);
if (ret)
return ERR_PTR(ret);
mutex_lock(&vc4->bo_lock); mutex_lock(&vc4->bo_lock);
bo->label = VC4_BO_TYPE_KERNEL; bo->label = VC4_BO_TYPE_KERNEL;
......
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