- 24 May, 2012 6 commits
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Ben Skeggs authored
Signed-off-by:Ben Skeggs <bskeggs@redhat.com>
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Ben Skeggs authored
The binary driver appears to do various bits and pieces of the memory clock frequency change at different times, depending on the particular transition that's occuring. I've attempted to replicate this here for div->pll, pll->div and div->div transitions. With some additional (patches upcoming) magic regs being bashed, this allows me to correctly transition between all 3 perflvls on NVS300. pll->pll transitions will *not* work correctly at the moment, pending me tricking the binary driver into doing one and seeing how to correctly handle it. This patch also handles (hopefully) 0x1110e0, which appears to need changing depending on whether in PLL or divider mode.. Maybe. We'll see. Signed-off-by: -
Ben Skeggs authored
Signed-off-by: -
Ben Skeggs authored
The reg calculation may get moved elsewhere at some point, but lets figure out what exactly we need to do first. Signed-off-by: -
Ben Skeggs authored
This gets us a start on memory timings. Signed-off-by: -
Ben Skeggs authored
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- 23 May, 2012 11 commits
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Dave Airlie authored
Reported-by: wfg@linux.intel.com Signed-off-by:Dave Airlie <airlied@redhat.com>
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Dave Airlie authored
these functions and the table can all be static/static const. Reported-by: wfg@linux.intel.com Signed-off-by: -
Dave Airlie authored
New drivers merged after changes were done in prime TTM code. Fix build. Signed-off-by: -
ssh://people.freedesktop.org/~airlied/linuxDave Airlie authored
* 'prime-merge' of ssh://people.freedesktop.org/~airlied/linux: drm/radeon: add PRIME support (v2) i915: add dmabuf/prime buffer sharing support. nouveau: add PRIME support ttm: add prime sharing support to TTM (v2) udl: add prime fd->handle support. drm/prime: add exported buffers to current fprivs imported buffer list (v2) drm/prime: introduce sg->pages/addr arrays helper
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Alex Deucher authored
This adds prime->fd and fd->prime support to radeon. It passes the sg object to ttm and then populates the gart entries using it. Compile tested only. v2: stub kmap + use new helpers + add reimporting Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Jerome Glisse <jglisse@redhat.com> Reviewed-by:
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Daniel Vetter authored
This adds handle->fd and fd->handle support to i915, this is to allow for offloading of rendering in one direction and outputs in the other. v2 from Daniel Vetter: - fixup conflicts with the prepare/finish gtt prep work. - implement ppgtt binding support. Note that we have squat i-g-t testcoverage for any of the lifetime and access rules dma_buf/prime support brings along. And there are quite a few intricate situations here. Also note that the integration with the existing code is a bit hackish, especially around get_gtt_pages and put_gtt_pages. It imo would be easier with the prep code from Chris Wilson's unbound series, but that is for 3.6. Also note that I didn't bother to put the new prepare/finish gtt hooks to good use by moving the dma_buf_map/unmap_attachment calls in there (like we've originally planned for). Last but not least this patch is only compile-tested, but I've changed very little compared to Dave Airlie's version. So there's a decent chance v2 on drm-next works as well as v1 on 3.4-rc. v3: Right when I've hit sent I've noticed that I've screwed up one obj->sg_list (for dmar support) and obj->sg_table (for prime support) disdinction. We should be able to merge these 2 paths, but that's material for another patch. v4: fix the error reporting bugs pointed out by ickle. v5: fix another error, and stop non-gtt mmaps on shared objects stop pread/pwrite on imported objects, add fake kmap Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Dave Airlie authored
This adds prime->fd and fd->prime support to nouveau, it passes the SG object to TTM, and then populates the GART entries using it. v2: add stubbed kmap + use new function to fill out pages array for faulting + add reimport test. Reviewed-by:
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Dave Airlie authored
This adds the ability for ttm common code to take an SG table and use it as the backing for a slave TTM object. The drivers can then populate their GTT tables using the SG object. v2: make sure to setup VM for sg bos as well. Reviewed-by:
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Dave Airlie authored
udl can only be used as an output offload so doesn't need to support handle->fd direction. Reviewed-by:
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Dave Airlie authored
If userspace attempts to import a buffer it exported on the same device, we need to return the same GEM handle for it, not a new handle pointing at the same GEM object. v2: move removals into a single fn, no need to set to NULL. (Chris Wilson) Signed-off-by: -
Dave Airlie authored
the ttm drivers need this currently, in order to get fault handling working and efficient. It also allows addrs to be NULL for devices like udl. Reviewed-by:
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- 22 May, 2012 20 commits
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Rob Clark authored
The omapdrm driver uses this for setting per-overlay rotation. It is likely also useful for setting YUV->RGB colorspace conversion matrix, etc. Signed-off-by:
Rob Clark <rob@ti.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Rob Clark authored
A bitmask property is similar to an enum. The enum value is a bit position (0-63), and valid property values consist of a mask of zero or more of (1 << enum_val[n]). [airlied: 1LL -> 1ULL] Signed-off-by:
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Dave Airlie authored
Merge branch 'exynos-drm-next' of git://git.infradead.org/users/kmpark/linux-samsung into drm-core-next * 'exynos-drm-next' of git://git.infradead.org/users/kmpark/linux-samsung: drm/exynos: add G2D driver drm/exynos: added vp scaling feature for hdmi drm/exynos: added source size to overlay structure drm/exynos: add additional display mode for hdmi drm/exynos: enable dvi mode for dvi monitor drm/exynos: fixed wrong pageflip finish event for interlace mode drm/exynos: add PM functions for hdmi and mixer drm/exynos: add dpms for hdmi drm/exynos: use threaded irq for hdmi hotplug drm/exynos: use platform_get_irq_byname for hdmi drm/exynos: cleanup for hdmi platform data drm/exynos: added a feature to get gem buffer information. drm/exynos: added drm prime feature. drm/exynos: added cache attribute support for gem. vgaarb: Provide dummy default device functions
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Laurent Pinchart authored
Drivers for hardware without gamma support should not be forced to implement a no-op gamma set operation. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Cc: Rob Clark <rob.clark@linaro.org> Signed-off-by:
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Laurent Pinchart authored
The DRM mode config functions structure declared by drivers and pointed to by the drm_mode_config funcs field is never modified. Make it a const pointer. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Laurent Pinchart authored
The GEM vm operations structure is passed to the VM core that stores it in a const field. There vm operations structures can thus be const in DRM as well. Signed-off-by:
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Laurent Pinchart authored
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Laurent Pinchart authored
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Laurent Pinchart authored
A race condition exists in drm_vblank_cleanup() if the vblank disable timer callback runs after freeing the memory that its callback function tries to access. Fix this by deleting the timer synchronously. Signed-off-by:
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Corentin Chary authored
The power field was never correctly initialized. [airlied: just took the two drm specific bits] Signed-off-by:
Corentin Chary <corentin.chary@gmail.com> Signed-off-by:
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Adam Jackson authored
(airlied: v2: fix missing struct - fixes compile) Signed-off-by:
Adam Jackson <ajax@redhat.com> Signed-off-by:
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Adam Jackson authored
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Adam Jackson authored
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Adam Jackson authored
Low four bits are downstream port count. High bit indicates peer OUI support. OUI matching will allow us to do additional per-sink handling for things like DP->VGA bandwidth limits or (hopefully) the iMac-as- display hack. Signed-off-by:
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Adam Jackson authored
DisplayPort has an escape hatch by which sources and sinks can identify each other. We would prefer not to notice this, but I suspect we're going to need to. Signed-off-by:
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Alan Cox authored
Reported-by:
Guillaume Clément <guillaume@baobob.org> Signed-off-by:
Alan Cox <alan@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by:
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Patrik Jakobsson authored
Poulsbo needs a physical address in the cursor base register. We allocate a stolen memory buffer and copy the cursor image provided by userspace into it. When/If we get our own userspace driver we can map this stolen memory directly. The patch also adds a mark in chip ops so we can identify devices that has this requirement. Signed-off-by:
Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Signed-off-by:
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Alan Cox authored
Some devices don't have a panel connected to LVDS and thus will never power up. This patch checks the power sequence progress bits in PP_STATUS to prevent an endless loop on such devices. Signed-off-by:
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Rafał Miłecki authored
This optmizes calls, registers reads and assignments. Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
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Dave Airlie authored
This seems to be wrong to me, spotted while thinking about dma-buf. Reviewed-by:
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- 21 May, 2012 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-next-2012-05-20' of git://people.freedesktop.org/~danvet/drm-intel into drm-core-next Daniel wrote: The last pull I'd like to squeeze into 3.5, safe for the hsw stuff mostly bugfixes: - last few patches for basic hsw enabling (Eugeni, infoframe support by Paulo) - Fix up infoframe support, we've hopefully squashed all the cargo-culting in there (Paulo). Among all the issues, this finally fixes some of the infoframe regressions seen on g4x and snb systems. - Fixup sdvo infoframe support, this fixes a regression from 2.6.37. - Correctly enable semaphores on snb, we've enabled it already for 3.5, but the dmar check was slightly wrong. - gen6 irq fixlets from Chris. - disable gmbus on i830, the hw seems to be simply broken. - fix up the pch pll fallout (Chris & me). - for_each_ring macro from Chris - I've figured I'll merge this now to avoid backport pain. - complain when the rps state isn't what we expect (Chris). Note that this is shockingly easy to hit and hence pretty much will cause a regression report. But it only tells us that the gpu turbo state got out of whack, a problem we know off since a long time (it cause the gpu to get stuck a a fixed frequency, usually the lowest one). Chris is working on a fix, but we haven't yet found a magic formula that works perfectly (only patches that massively reduce the frequency of this happening). - MAINTAINERS patch, I'm now officially the guy to beat up." * tag 'drm-intel-next-2012-05-20' of git://people.freedesktop.org/~danvet/drm-intel: (57 commits) drm/i915: IBX has a fixed pch pll to pch pipe mapping drm/i915: implement hsw_write_infoframe drm/i915: small hdmi coding style cleanups drm/i915: fixup infoframe support for sdvo drm/i915: Enable the PCH PLL for all generations after link training drm/i915: Convert BUG_ON(!pll->active) and friends to a WARN drm/i915: don't clobber the pipe param in sanitize_modesetting drm/i915: disable gmbus on i830 drm/i915: Replace the feature tests for BLT/BSD with ring init checks drm/i915: Check whether the ring is initialised prior to dispatch drm/i915: Introduce for_each_ring() macro drm/i915: Assert that the transcoder is indeed off before modifying it drm/i915: hook Haswell devices in place drm/i915: prepare HDMI link for Haswell drm/i915: move HDMI structs to shared location drm/i915: add WR PLL programming table drm/i915: add support for DDI-controlled digital outputs drm/i915: detect digital outputs on Haswell drm/i915: program iCLKIP on Lynx Point drm/i915: program WM_LINETIME on Haswell ...
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- 20 May, 2012 2 commits
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Daniel Vetter authored
This should fix breakage introduced in commit ee7b9f93 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Fri Apr 20 17:11:53 2012 +0100 drm/i915: manage PCH PLLs separately from pipes v2: Add a DRM_DEBUG_KMS message to explain why a given pll was selected, suggested by Chris Wilson. v3: Actually run git add. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49712Signed-Off-by:
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Paulo Zanoni authored
Both the control and data registers are completely different now. Signed-off-by:
Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by:
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