1. 16 Dec, 2021 8 commits
  2. 15 Dec, 2021 1 commit
  3. 14 Dec, 2021 3 commits
    • Thomas Gleixner's avatar
      Merge branch 'irq/urgent' into irq/msi · 09eb3ad5
      Thomas Gleixner authored
      to pick up the PCI/MSI-x fixes.
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      09eb3ad5
    • Thomas Gleixner's avatar
      PCI/MSI: Clear PCI_MSIX_FLAGS_MASKALL on error · 94185adb
      Thomas Gleixner authored
      PCI_MSIX_FLAGS_MASKALL is set in the MSI-X control register at MSI-X
      interrupt setup time. It's cleared on success, but the error handling path
      only clears the PCI_MSIX_FLAGS_ENABLE bit.
      
      That's incorrect as the reset state of the PCI_MSIX_FLAGS_MASKALL bit is
      zero. That can be observed via lspci:
      
              Capabilities: [b0] MSI-X: Enable- Count=67 Masked+
      
      Clear the bit in the error path to restore the reset state.
      
      Fixes: 43855395 ("PCI/MSI: Enable and mask MSI-X early")
      Reported-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Tested-by: default avatarStefan Roese <sr@denx.de>
      Cc: linux-pci@vger.kernel.org
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: stable@vger.kernel.org
      Link: https://lore.kernel.org/r/87tufevoqx.ffs@tglx
      94185adb
    • Stefan Roese's avatar
      PCI/MSI: Mask MSI-X vectors only on success · 83dbf898
      Stefan Roese authored
      Masking all unused MSI-X entries is done to ensure that a crash kernel
      starts from a clean slate, which correponds to the reset state of the
      device as defined in the PCI-E specificion 3.0 and later:
      
       Vector Control for MSI-X Table Entries
       --------------------------------------
      
       "00: Mask bit:  When this bit is set, the function is prohibited from
                       sending a message using this MSI-X Table entry.
                       ...
                       This bit’s state after reset is 1 (entry is masked)."
      
      A Marvell NVME device fails to deliver MSI interrupts after trying to
      enable MSI-X interrupts due to that masking. It seems to take the MSI-X
      mask bits into account even when MSI-X is disabled.
      
      While not specification compliant, this can be cured by moving the masking
      into the success path, so that the MSI-X table entries stay in device reset
      state when the MSI-X setup fails.
      
      [ tglx: Move it into the success path, add comment and amend changelog ]
      
      Fixes: aa8092c1d1f1 ("PCI/MSI: Mask all unused MSI-X entries")                                                                                                                                                                                                                 
      Signed-off-by: default avatarStefan Roese <sr@denx.de>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Cc: linux-pci@vger.kernel.org
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Cc: Marek Vasut <marex@denx.de>
      Cc: stable@vger.kernel.org
      Link: https://lore.kernel.org/r/20211210161025.3287927-1-sr@denx.de
      83dbf898
  4. 12 Dec, 2021 14 commits
  5. 11 Dec, 2021 14 commits