- 16 Aug, 2022 40 commits
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Rodrigo Siqueira authored
We have some old code associated with DML, which we had plans to use, but at some point, we just moved away from it. This commit removes the dml_wrapper* files since they are not used anymore. Reported-by:
Magali Lemes <magalilemes00@gmail.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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shaoyunl authored
The second jump table is required on live migration or mulitple VF configuration on Aldebaran. With this implemented, the first level jump table(hw used) will be same, mec fw internal will use the second level jump table jump to the real functionality implementation. so the different VF can load different version of MEC as long as they support sjt Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Acked-by:
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Hamza Mahfooz authored
Currently, we are using soc._clock_tmp[] to temporarily store and modify data from soc.clock_limits[] before copying it back into soc.clock_limits[] (because modifying data directly in soc.clock_limits[] causes unintended behavior). However, this approach has a number of downsides, such as: 1. struct _vcs_dpi_soc_bounding_box_st's creation/destruction aren't well defined (which could mean more unintended behavior). 2. Throwing "temp" varibles in structs everywhere doesn't make for a particularly readable codebase. For these reasons, we should get rid of soc._clock_tmp[] by defining a struct scratch within struct dc that, contains within it all of the temporary variables (including _clock_tmp[]) such that it is obvious how they are intended to be used. Co-authored-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Hamza Mahfooz authored
Currently, we only attempt to setup DSC at the virtual DPCD port, however many modern displays come with DSC support and MST hubs can now support DSC pass-through. So, to more optimally make use of the available bandwidth, use DSC pass-through when possible by adding DSC pass-through enablement support into the DSC enable sequence. Signed-off-by:
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Hamza Mahfooz authored
Add a mode validation routine for DSC pass-through. Both the link from source to hub, and the link from hub to monitor are checked, according to the current link training result and full pbn returned by enum path resource sideband message. Pick up the minimum value as the bandwidth bottleneck for the end to end link bandwidth constraint, and check if the maximum DSC decompression bandwidth can fit. v2: squash in DSC CONFIG_DRM_AMD_DC_DCN compilation fix (Hamza) Co-authored-by:
Fangzhi Zuo <Jerry.Zuo@amd.com> Signed-off-by:
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Hamza Mahfooz authored
Currently, there is no way to identify if DSC pass-through can be enabled and what aux DSC pass-through requests ought to be sent to. So, add a variable to struct drm_dp_mst_port that keeps track of the aforementioned information. Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Melissa Wen authored
AMD GPU display manager (DM) maps DRM pixel blend modes (None, Pre-multiplied, Coverage) to MPC hw blocks through blend configuration options. Describe relevant elements and how to set and test them to get the expected DRM blend mode on DCN hw. v2: - add ref tag (Tales) Signed-off-by:
Melissa Wen <mwen@igalia.com> Reviewed-by:
Tales Aparecida <tales.aparecida@gmail.com> Reviewed-by:
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Melissa Wen authored
Describe structs and enums used to set blend mode properties to MPC blocks. Some pieces of information are already available as code comments, and were just formatted. Others were collected and summarised from discussions on AMD issue tracker[1][2]. [1] https://gitlab.freedesktop.org/drm/amd/-/issues/1734 [2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769 v2: - fix typos (Tales) - add MPCC to MPC entry in the glossary Signed-off-by:
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Melissa Wen authored
Add details about color correction capabilities and explain a bit about differences between DC hw generations and also how they are mapped between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted to svg from the original png) is included to illustrate it. They were obtained from a discussion[1] in the amd-gfx mailing list. [1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/ v1: - remove redundant comments (Harry) - fix typos (Harry) v2: - reword introduction of color section - add co-dev tag for Harry - who provided most of the info - fix typos (Tales) - describe missing struct parameters (Tales and Siqueira) Co-developed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Melissa Wen authored
AMDGPU DM maps DRM color management properties (degamma, ctm and gamma) to DC color correction entities. Part of this mapping is already documented as code comments and can be converted as kernel docs. v2: - rebase to amd-staging-drm-next - fix typos (Tales) - undo kernel-docs inside functions (Tales) Signed-off-by:
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Rodrigo Siqueira authored
Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
The timing programming inside DCN is far from trivial, it has multiple parameters associated with that, and the lack of documentation does not help comprehend this already complicated topic. This commit tries to improve this situation by expanding the documentation of dc_crtc_timing and the VTG program function. Reviewed-by:
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Rodrigo Siqueira authored
In the DCN code, we can find some references to three different pipe split policies but no clear description. This commit adds some kernel-doc that explains more about these options and a little bit of their impact. Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Rodrigo Siqueira authored
Reviewed-by:
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Victor Zhao authored
In multi container use case, reset time is important, so skip ring tests and cp halt wait during ip suspending for reset as they are going to fail and cost more time on reset v2: add a hang flag to indicate the reset comes from a job timeout, skip ring test and cp halt wait in this case v3: move hang flag to adev Signed-off-by:
Victor Zhao <Victor.Zhao@amd.com> Acked-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Victor Zhao authored
For some hang caused by slow tests, engine cannot be stopped which may cause resume failure after reset. In this case, force halt engine by reverting context addresses Signed-off-by:
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Victor Zhao authored
Save and restore gfxhub regs as they will be reset during mode 2 Signed-off-by:
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Victor Zhao authored
Introduce amdgpu_reset_level debugfs in order to help debug and test specific type of reset. Also helps blocking unwanted type of resets. By default, mode2 reset will not be enabled v2: make this debugfs in adev and use debugfs_create_u32 Signed-off-by:
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Victor Zhao authored
- introduce AMDGPU_SKIP_MODE2_RESET flag - let mode2 reset fallback to default reset method if failed v2: move this part out from the asic specific part Signed-off-by:
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Victor Zhao authored
To meet the requirement for multi container usecase which needs a quicker reset and not causing VRAM lost, adding the Mode2 reset handler for sienna_cichlid. v2: move skip mode2 flag part separately v3: remove the use of asic_reset_res Signed-off-by:
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Michel Dänzer authored
This reverts commit 4c763180. Triggered GFX hangs with GNOME Wayland on Navi 21. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2117Signed-off-by:
Michel Dänzer <mdaenzer@redhat.com> Signed-off-by:
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Maíra Canal authored
If amdgpu_cs_vm_handling returns r != 0, then it will unlock the bo_list_mutex inside the function amdgpu_cs_vm_handling and again on amdgpu_cs_parser_fini. This problem results in the following use-after-free problem: [ 220.280990] ------------[ cut here ]------------ [ 220.281000] refcount_t: underflow; use-after-free. [ 220.281019] WARNING: CPU: 1 PID: 3746 at lib/refcount.c:28 refcount_warn_saturate+0xba/0x110 [ 220.281029] ------------[ cut here ]------------ [ 220.281415] CPU: 1 PID: 3746 Comm: chrome:cs0 Tainted: G W L ------- --- 5.20.0-0.rc0.20220812git7ebfc85e.10.fc38.x86_64 #1 [ 220.281421] Hardware name: System manufacturer System Product Name/ROG STRIX X570-I GAMING, BIOS 4403 04/27/2022 [ 220.281426] RIP: 0010:refcount_warn_saturate+0xba/0x110 [ 220.281431] Code: 01 01 e8 79 4a 6f 00 0f 0b e9 42 47 a5 00 80 3d de 7e be 01 00 75 85 48 c7 c7 f8 98 8e 98 c6 05 ce 7e be 01 01 e8 56 4a 6f 00 <0f> 0b e9 1f 47 a5 00 80 3d b9 7e be 01 00 0f 85 5e ff ff ff 48 c7 [ 220.281437] RSP: 0018:ffffb4b0d18d7a80 EFLAGS: 00010282 [ 220.281443] RAX: 0000000000000026 RBX: 0000000000000003 RCX: 0000000000000000 [ 220.281448] RDX: 0000000000000001 RSI: ffffffff988d06dc RDI: 00000000ffffffff [ 220.281452] RBP: 00000000ffffffff R08: 0000000000000000 R09: ffffb4b0d18d7930 [ 220.281457] R10: 0000000000000003 R11: ffffa0672e2fffe8 R12: ffffa058ca360400 [ 220.281461] R13: ffffa05846c50a18 R14: 00000000fffffe00 R15: 0000000000000003 [ 220.281465] FS: 00007f82683e06c0(0000) GS:ffffa066e2e00000(0000) knlGS:0000000000000000 [ 220.281470] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 220.281475] CR2: 00003590005cc000 CR3: 00000001fca46000 CR4: 0000000000350ee0 [ 220.281480] Call Trace: [ 220.281485] <TASK> [ 220.281490] amdgpu_cs_ioctl+0x4e2/0x2070 [amdgpu] [ 220.281806] ? amdgpu_cs_find_mapping+0xe0/0xe0 [amdgpu] [ 220.282028] drm_ioctl_kernel+0xa4/0x150 [ 220.282043] drm_ioctl+0x21f/0x420 [ 220.282053] ? amdgpu_cs_find_mapping+0xe0/0xe0 [amdgpu] [ 220.282275] ? lock_release+0x14f/0x460 [ 220.282282] ? _raw_spin_unlock_irqrestore+0x30/0x60 [ 220.282290] ? _raw_spin_unlock_irqrestore+0x30/0x60 [ 220.282297] ? lockdep_hardirqs_on+0x7d/0x100 [ 220.282305] ? _raw_spin_unlock_irqrestore+0x40/0x60 [ 220.282317] amdgpu_drm_ioctl+0x4a/0x80 [amdgpu] [ 220.282534] __x64_sys_ioctl+0x90/0xd0 [ 220.282545] do_syscall_64+0x5b/0x80 [ 220.282551] ? futex_wake+0x6c/0x150 [ 220.282568] ? lock_is_held_type+0xe8/0x140 [ 220.282580] ? do_syscall_64+0x67/0x80 [ 220.282585] ? lockdep_hardirqs_on+0x7d/0x100 [ 220.282592] ? do_syscall_64+0x67/0x80 [ 220.282597] ? do_syscall_64+0x67/0x80 [ 220.282602] ? lockdep_hardirqs_on+0x7d/0x100 [ 220.282609] entry_SYSCALL_64_after_hwframe+0x63/0xcd [ 220.282616] RIP: 0033:0x7f8282a4f8bf [ 220.282639] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <89> c2 3d 00 f0 ff ff 77 18 48 8b 44 24 18 64 48 2b 04 25 28 00 00 [ 220.282644] RSP: 002b:00007f82683df410 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 220.282651] RAX: ffffffffffffffda RBX: 00007f82683df588 RCX: 00007f8282a4f8bf [ 220.282655] RDX: 00007f82683df4d0 RSI: 00000000c0186444 RDI: 0000000000000018 [ 220.282659] RBP: 00007f82683df4d0 R08: 00007f82683df5e0 R09: 00007f82683df4b0 [ 220.282663] R10: 00001d04000a0600 R11: 0000000000000246 R12: 00000000c0186444 [ 220.282667] R13: 0000000000000018 R14: 00007f82683df588 R15: 0000000000000003 [ 220.282689] </TASK> [ 220.282693] irq event stamp: 6232311 [ 220.282697] hardirqs last enabled at (6232319): [<ffffffff9718cd7e>] __up_console_sem+0x5e/0x70 [ 220.282704] hardirqs last disabled at (6232326): [<ffffffff9718cd63>] __up_console_sem+0x43/0x70 [ 220.282709] softirqs last enabled at (6232072): [<ffffffff970ff669>] __irq_exit_rcu+0xf9/0x170 [ 220.282716] softirqs last disabled at (6232061): [<ffffffff970ff669>] __irq_exit_rcu+0xf9/0x170 [ 220.282722] ---[ end trace 0000000000000000 ]--- Therefore, remove the mutex_unlock from the amdgpu_cs_vm_handling function, so that amdgpu_cs_submit and amdgpu_cs_parser_fini can handle the unlock. Fixes: 90af0ca0 ("drm/amdgpu: Protect the amdgpu_bo_list list with a mutex v2") Reported-by:
Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Maíra Canal <mairacanal@riseup.net> Signed-off-by:
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Mukul Joshi authored
There are no backing hardware registers for ih_soft ring. As a result, don't try to access hardware registers for read and write pointers when processing interrupts on the IH soft ring. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Shane Xiao authored
Add secure display TA load for Renoir Signed-off-by:
Shane Xiao <shane.xiao@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] For SubVP scaling cases, we must include the scaling info as part of the cmd. This is required when converting OTG line to HUBP line for the MALL_START_LINE programming. Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Brian Chang <Brian.Chang@amd.com> Signed-off-by:
Alvin Lee <Alvin.Lee2@amd.com> Tested-by:
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Khalid Masum authored
There is no point in returning an int here. It only returns 0 which the caller never uses. Therefore return void and remove the unnecessary assignment. Addresses-Coverity: 1504988 ("Unused value") Fixes: 8da1170a ("drm/amdgpu: add VCN4 ip block support") Reviewed-by:Ruijing Dong <ruijing.dong@amd.com> Suggested-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
Khalid Masum <khalid.masum.92@gmail.com> Signed-off-by:
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Andrey Strachuk authored
Local variable 'rq' is initialized by an address of field of drm_sched_job, so it does not make sense to compare 'rq' with NULL. Found by Linux Verification Center (linuxtesting.org) with SVACE. Reviewed-by:
Andrey Strachuk <strochuk@ispras.ru> Fixes: 7c6e68c7 ("drm/amdgpu: Avoid HW GPU reset for RAS.") Signed-off-by:
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Harish Kasiviswanathan authored
Was missing. Add it. Signed-off-by:
Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Samson Tam authored
[Why & How] Add GC_11_0_3_A0 as a chip revision to the DCN32 family Reviewed-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Charlene Liu authored
[why] this is to ensure that driver will not reprogram hvm_prefetch_req again if it is done. Reviewed-by:
Martin Leung <Martin.Leung@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Alvin Lee authored
[Description] Use pitch when calculating size to cache in MALL Reviewed-by:
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Alvin Lee authored
[Description] Don't set DSC bit for phantom pipes, not required since phantom pipe don't have any actual output Reviewed-by:
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Nicholas Kazlauskas authored
[Why & How] Depending on how the clock table is constructed from PMFW we can run into issues where we don't think we have enough bandwidth available due to FCLK too low - eg. when the FCLK table contains invalid entries or a single entry. We should always pick up the maximum clocks for each state as a final state in this case to prevent validation from failing if the table is malformed. We should also contain sensible defaults in the case where values are invalid. Redfine the clock table structures by adding a 314 prefix to make debugging these issues easier by avoiding symbol name clashes. Overall this policy more closely aligns to how we did things for 315, but because of how the voltage rail is setup we should favor keeping DCFCLK low rather than DISPCLK or DPPCLK - so use the max for those in every entry. Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Chaitanya Dhere authored
[Why] Recent backport from opensource broke the Nightly tool build that tests DC and DML for bugs and regressions. This was because the backport had a header inclusion that was not consistent with the AMD style of including headers was allowed to be merged back in DML code that caused tool compilation failures. [How] Modify the way in which the header file in included so that it is consistent with AMD style of including headers. This then automatically fixes the tool compilation process and also helps maintain the code quality and consistency. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Tested-by:
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Tom Chung authored
[Why] Pipes for MPO primary and overlay will be power down and power up during plug/unplug external monitor while MPO video playback. But the pipes were the same after plug/unplug and should not need to be power down and power up or it will make page flip interrupt disabled and cause hang issue. [How] Add pipe split change condition that not only check the top pipe pointer but also check the index of top pipe if both top pipes are available. Reviewed-by:
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Daniel Miess authored
[Why] Need a way to retain default clock table to aid the investigation into why 8k@30 display not lighting up on dcn314 [How] Use flag to prevent execution of bw_params helper function and function for updating bw_bounding_box Reviewed-by:
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Dusica Milinkovic authored
[Why] During multi-vf executing benchmark (Luxmark) observed kiq error timeout. It happenes because all of VFs do the tlb invalidation at the same time. Although each VF has the invalidate register set, from hardware side the invalidate requests are queue to execute. [How] In case of 12 VF increase timeout on 12*100ms Signed-off-by:
Dusica Milinkovic <Dusica.Milinkovic@amd.com> Acked-by:
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Josip Pavic authored
[Why & How] Increase width of some variables to avoid comparing integers of different widths. Reviewed-by:
Josip Pavic <Josip.Pavic@amd.com> Tested-by:
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