1. 03 Sep, 2024 2 commits
  2. 02 Sep, 2024 3 commits
  3. 30 Aug, 2024 3 commits
  4. 29 Aug, 2024 7 commits
  5. 28 Aug, 2024 7 commits
  6. 23 Aug, 2024 3 commits
  7. 19 Aug, 2024 5 commits
  8. 14 Aug, 2024 4 commits
  9. 13 Aug, 2024 1 commit
  10. 02 Aug, 2024 2 commits
    • Mark Brown's avatar
      spi: Add dummy definitions for ACPI lookup functions · d196c714
      Mark Brown authored
      Merge series from Richard Fitzgerald <rf@opensource.cirrus.com>:
      
      Provide empty versions of acpi_spi_count_resources(),
      acpi_spi_device_alloc() and acpi_spi_find_controller_by_adev()
      if the real functions are not being built.
      
      This commit fixes two problems with the original definitions:
      
      1) There wasn't an empty version of these functions
      2) The #if only depended on CONFIG_ACPI. But the functions are implemented
         in the core spi.c so CONFIG_SPI_MASTER must also be enabled for the real
         functions to exist.
      d196c714
    • Richard Fitzgerald's avatar
      spi: Add empty versions of ACPI functions · 90ec3a8a
      Richard Fitzgerald authored
      Provide empty versions of acpi_spi_count_resources(),
      acpi_spi_device_alloc() and acpi_spi_find_controller_by_adev()
      if the real functions are not being built.
      
      This commit fixes two problems with the original definitions:
      
      1) There wasn't an empty version of these functions
      2) The #if only depended on CONFIG_ACPI. But the functions are implemented
         in the core spi.c so CONFIG_SPI_MASTER must also be enabled for the real
         functions to exist.
      Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
      Link: https://patch.msgid.link/20240802152215.20831-2-rf@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      90ec3a8a
  11. 31 Jul, 2024 1 commit
  12. 30 Jul, 2024 1 commit
  13. 29 Jul, 2024 1 commit
    • Mark Brown's avatar
      Marvell HW overlay support for Cadence xSPI · 5cb7651f
      Mark Brown authored
      Merge series from Witold Sadowski <wsadowski@marvell.com>:
      
      This patch series adds support for the second version of the Marvell
      hardware overlay for the Cadence xSPI IP block. The overlay is a hardware
      change made around the original xSPI block. It extends xSPI features with
      clock configuration, interrupt masking, and full-duplex, variable-length SPI
      operations.
      
      These functionalities allow the xSPI block to operate not only with memory
      devices but also with simple SPI devices and TPM devices.
      
      Example ACPI entry:
            Device (SPI0) {
              Name (_HID, "PRP0001")          // ACPI_DT_NAMESPACE_HID
              Name (_UID, 0)
              Name (_DDN, "SPI controller 0")
              Name (_CCA, ONE)
      
              Method (_STA) {Return (0xF)}
      
              Name (_CRS, ResourceTemplate() {
      
                QWordMemory ( ResourceConsumer,// ResourceUsage
                              PosDecode,       // Decode
                              MinFixed,        // MinType
                              MaxFixed,        // MaxType
                              NonCacheable,    // MemType
                              ReadWrite,       // ReadWriteType
                              0,               // AddressGranularity
                              0x804000000000,  // MinAddress
                              0x804000001037,  // MaxAddress
                              0,               // AddressTranslation
                              0x1038)          // AddressLength
      
                QWordMemory ( ResourceConsumer,// ResourceUsage
                              PosDecode,       // Decode
                              MinFixed,        // MinType
                              MaxFixed,        // MaxType
                              NonCacheable,    // MemType
                              ReadWrite,       // ReadWriteType
                              0,               // AddressGranularity
                              0x804010000000,  // MinAddress
                              0x804010000007,  // MaxAddress
                              0,               // AddressTranslation
                              0x8)             // AddressLength
      
                QWordMemory ( ResourceConsumer,// ResourceUsage
                              PosDecode,       // Decode
                              MinFixed,        // MinType
                              MaxFixed,        // MaxType
                              NonCacheable,    // MemType
                              ReadWrite,       // ReadWriteType
                              0,               // AddressGranularity
                              0x804000002000,  // MinAddress
                              0x804000004027,  // MaxAddress
                              0,               // AddressTranslation
                              0x2028)          // AddressLength
      
                QWordMemory ( ResourceConsumer,// ResourceUsage
                  PosDecode,       // Decode
                  MinFixed,        // MinType
                  MaxFixed,        // MaxType
                  NonCacheable,    // MemType
                  ReadWrite,       // ReadWriteType
                  0,               // AddressGranularity
                  0x804000008000,  // MinAddress
                  0x804000008237,  // MaxAddress
                  0,               // AddressTranslation
                  0x238)           // AddressLength
      
                Interrupt(ResourceConsumer, Edge, ActiveHigh, Exclusive) { 0x7A }
              })
      
              Name (_DSD, Package() {
                  ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
                  Package () {
                      Package () { "compatible", "marvell,cn10-xspi-nor"},
                      Package () { "reg", 0x8040},
                  }
              })
            } // SPI0
      5cb7651f