- 25 Jan, 2019 40 commits
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David Francis authored
[Why] Underscan and ABM are connector properties but require updates to DC stream state. Previously, on updates to these properties the affected stream and all its planes were committed. This is unnecessary; only a few fields on the stream need to be changed. [How] If scaling or ABM have changed, change the stream and create a stream update with those changes. Call DC with only those fields. Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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David Francis authored
[Why] DC was assuming that any surface_update->scaling_info meant the update was at least medium. However, if nothing has changed there is no scaling to program, so there is no problem with the update being fast [How] If every update flag is not set, the update is fast Signed-off-by:
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Eryk Brol authored
Virtual memory allows display to support flipping to surfaces which are not allocated contiguously in memory with physical addresses, instead a 1-4 level page table is used. This is beneficial because it allows the scattering of large surfaces to improve memory efficiency and security. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Eryk Brol authored
[Why] Change DCN10 hubbub to use hubbub as a base and allow all future DCN hubbubs to do the same instead of using DCN10_hubbub. This increases readability and doesn't require future hubbubs to inherit anything other than the base hubbub struct. [How] Create separate DCN10_hubbub struct which uses the hubbub struct as a base. Signed-off-by:
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hersen wu authored
[Why] For fastboot, Bios will light up eDP before SW driver is loaded. SW driver will check if eDP is lit by bios through reading the BIOS_SCRATCH_3 register. If lit, SW driver will not power down eDP power and phy to save time. Definition of BIOS_SCRATCH_3 are missing for pre-raven asic. This causes eDP fast boot to not work property. For some eDP panels, even if dp tx sends NoVideoStream_flag =1 and dpcd 0x600=2, eDP rx may not handle properly. This may cause a short flash on screen. [How] Add definition of BIOS_SCRATCH_3 for all asic Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Expedite job deletion from ring mirror list to the HW fence signal callback instead from finish_work, together with waiting for all such fences to signal in drm_sched_stop we garantee that already signaled job will not be processed twice. Remove the sched finish fence callback and just submit finish_work directly from the HW fence callback. v2: Fix comments. v3: Attach hw fence cb to sched_job v5: Rebase Suggested-by:
Christian Koenig <Christian.Koenig@amd.com> Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Decauple sched threads stop and start and ring mirror list handling from the policy of what to do about the guilty jobs. When stoppping the sched thread and detaching sched fences from non signaled HW fenes wait for all signaled HW fences to complete before rerunning the jobs. v2: Fix resubmission of guilty job into HW after refactoring. v4: Full restart for all the jobs, not only from guilty ring. Extract karma increase into standalone function. v5: Rework waiting for signaled jobs without relying on the job struct itself as those might already be freed for non 'guilty' job's schedulers. Expose karma increase to drivers. v6: Use list_for_each_entry_safe_continue and drm_sched_process_job in case fence already signaled. Call drm_sched_increase_karma only once for amdgpu and add documentation. v7: Wait only for the latest job's fence. Suggested-by:
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Evan Quan authored
For those SKUs which support this feature only. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
MGPU fan boost related parameter is added. Signed-off-by:
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Alex Deucher authored
The power smu7 powerplay code is much more robust and has been the default for a while now. Remove the old code. Acked-by:
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Alex Deucher authored
Check if the device is root rather before attempting to see what speeds the pcie port supports. Fixes a crash with pci passthrough in a VM. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109366Reviewed-by:
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Alex Deucher authored
Add missing power_average to visible check for power attributes for APUs. Was missed before. Reviewed-by:
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Evan Quan authored
As the gfxclk for SMU11 can have at most 16 discrete levels. Signed-off-by:
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Evan Quan authored
BTC is needed before enabling all SMU features. Signed-off-by:
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Evan Quan authored
The SOC clock needs also to fit the new performance level. Signed-off-by:
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Evan Quan authored
No display related settings are needed on dpm level change. Signed-off-by:
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Evan Quan authored
No dpm level setting is needed when the request level is actually same as current. Signed-off-by:
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Jack Xiao authored
Replace the last bool type parameter with a general flags parameter, to make the last parameter be able to contain more information. v2: drop setting need_ctx_switch = false Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Kenneth Feng authored
gfxclk for OD setting is limited to 1980M for non-acg ASICs of Vega10 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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wentalou authored
sriov would meet guest driver load failure, if calling amdgpu_asic_reset in amdgpu_device_init. sriov should skip asic_reset in device_init. Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Acked-by:
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Alex Deucher authored
Needs ATPX rather than _PR3 for dGPU power control. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=202263Reviewed-by:
Jim Qu <Jim.Qu@amd.com> Signed-off-by:
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Evan Quan authored
Fix the APU judgement to make it really work as expected. Signed-off-by:
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Evan Quan authored
So that we do not need to check this in every internal function. Signed-off-by:
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Gustavo A. R. Silva authored
Replace kzalloc() function with its 2-factor argument form, kcalloc(). This patch replaces cases of: kzalloc(a * b, gfp) with: kcalloc(a, b, gfp) Also, improve the coding style and the use of sizeof during allocation by changing sizeof(struct dc_surface_update) and sizeof(struct dc_plane_state) to sizeof(*updates) and sizeof(*surfaces), correspondingly. This code was detected with the help of Coccinelle. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Christian König authored
This finally enables processing of ring 1 & 2. v2: fix copy&paste error Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Christian König authored
Previously we only added the ring buffer memory, now add the handling as well. Signed-off-by:
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Christian König authored
The entries are ignored for now, but it at least stops crashing the hardware when somebody tries to push something to the other IH rings. v2: limit ring size, add TODO comment v3: only program rings if they are actually allocated v4: limit the ring init to Vega10 Signed-off-by:
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Christian König authored
Otherwise we run into a non-retry fault on access. It seems to be a hardware bug that the executable bit has higher priority than the valid bit. v2: handle clears as well Signed-off-by:
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Christian König authored
Move the BO on the LRU only when it is actually moved by a DMA operation. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Tested-And-Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Evan Quan authored
User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by:
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Evan Quan authored
User can use "pp_dpm_fclk" to retrieve and adjust fclock power levels. V2: expose this interface for Vega20 and later ASICs only Signed-off-by:
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Evan Quan authored
User can use "pp_dpm_socclk" to retrieve and adjust SOC clock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by:
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Evan Quan authored
User can use "ppfeatures" sysfs interface to retrieve and set enabled powerplay features. V2: expose this feature for Vega10 and later dGPUs V3: squash in removal of unused variable (Alex) Signed-off-by:
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Chunming Zhou authored
if lru is changed, we cannot do bulk moving. v2: root bo isn't in bulk moving, skip its change. Signed-off-by:
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Chunming Zhou authored
allow driver do somethings when lru changed. v2: address Michel's comments. Signed-off-by:
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Aaron Liu authored
In some cases, psp response status is not 0 even there is no problem while the command is submitted. Some version of PSP FW doesn't write 0 to that field. So here we would like to only print a warning instead of an error during psp initialization to avoid breaking hw_init and it doesn't return -EINVAL. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Reviewed-by: Xiangliang Yu<Xiangliang.Yu@amd.com> Acked-by:
Feifei Xu <Feifei.Xu@amd.com> Reviewed-by:
Paul Menzel <pmenzel+amd-gfx@molgen.mpg.de> Signed-off-by:
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Oak Zeng authored
HW doorbell writing routing policy: writing to doorbell not in SDMA/IH/MM/ACV doorbell range will be routed to CP. So CP doorbell routing depends on doorbell range setting of above blocks. Setting doorbell range of above blocks earlier (soc15_common_hw_init) to make sure CP doorbell writing be routed to CP block. Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Oak Zeng authored
Different ASIC has different SDMA queue number so different SDMA doorbell range. Introduce an extra parameter to sdma_doorbell_range function and set sdma doorbell range correctly. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Signed-off-by:
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Oak Zeng authored
Different ASIC has different sdma doorbell range. Add a per device sdma_doorbell_range field and initialize it. Signed-off-by:
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Alex Deucher authored
Rather than just -1. Reviewed-by:
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