- 29 Nov, 2016 40 commits
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Ritesh Harjani authored
The newer msm sdhci's cores use a different DLL hardware for HS400. Update the configuration and calibration of the newer DLL block. The HS400 DLL block used previously is CDC LP 533 and requires programming multiple registers and waiting for configuration to complete and then enable it. It has about 18 register writes and two register reads. The newer HS400 DLL block is SDC4 DLL and requires two register writes for configuration and one register read to confirm that it is initialized. There is an additional register write to enable the power save mode for SDC4 DLL block. Signed-off-by:
Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by:
Krishna Konda <kkonda@codeaurora.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ritesh Harjani authored
In HS400 mode a new RCLK is introduced on the interface for read data transfers. The eMMC5.0 device transmits the read data to the host with respect to rising and falling edges of RCLK. In order to ensure correct operation of read data transfers in HS400 mode, the incoming RX data needs to be sampled by delayed version of RCLK. The CDCLP533 delay circuit shifts the RCLK by T/4. It needs to be initialized, configured and enabled once during HS400 mode switch and when operational voltage/clock is changed. Signed-off-by:
Venkat Gopalakrishnan <venkatg@codeaurora.org> Signed-off-by:
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Ritesh Harjani authored
Save the tuning phase once the tuning is performed. This phase value will be used while calibrating DLL for HS400 mode. Signed-off-by:
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Venkat Gopalakrishnan authored
The following msm platform specific changes are added to support HS400. - Allow tuning for HS400 mode. - Configure HS400 timing mode using the VENDOR_SPECIFIC_FUNC register. Signed-off-by:
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Ritesh Harjani authored
SDHC MSM controller need 2x clock for MCLK at GCC. Hence make required changes to have 2x clock for DDR timing modes. Signed-off-by:
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Ritesh Harjani authored
sdhci-msm controller may have different clk-rates for each bus speed mode. Thus implement set_clock callback for sdhci-msm driver. Signed-off-by:
Sahitya Tummala <stummala@codeaurora.org> Signed-off-by:
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Ritesh Harjani authored
Factor out sdhci_enable_clk from sdhci_set_clock and make it EXPORT_SYMBOL so that it can be called. Signed-off-by:
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Ritesh Harjani authored
sdhc-msm controller needs this SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN & SDHCI_QUIRK2_PRESET_VALUE_BROKEN to be set. Hence setting it. Signed-off-by:
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Ritesh Harjani authored
This add get_min_clock() and get_max_clock() callback for sdhci-msm. sdhci-msm min/max clocks may be different hence implement these callbacks. Signed-off-by:
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Venkat Gopalakrishnan authored
SDCC core with minor version >= 0x42 introduced new 14lpp DLL. This has additional requirements in the reset sequence for DLL tuning. Make necessary changes as needed. Without this patch we see below errors on such SDHC controllers sdhci_msm 7464900.sdhci: mmc0: DLL failed to LOCK mmc0: tuning execution failed: -110 Signed-off-by:
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Ritesh Harjani authored
Add "xo" value which is tcxo clock to sdhci-msm DT binding properties. Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Ritesh Harjani authored
This patch changes the poor style of writel/readl registers into more readable format. This avoid mixed style format of readl/writel in sdhci-msm driver. This patch also removes the one line comments which were present for above writel/readl, since they were of no help. Signed-off-by:
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Jaehoon Chung authored
"support-highspeed" was the obsoleted property. And "broken-cd" is not synopsys specific property. It can be referred to mmc.txt binding Documentation. Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> Acked-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
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Jaehoon Chung authored
The "clock-freq-min-max" property was deprecated. There is "max-frequency" property in drivers/mmc/core/host.c "max-frequency" can be replaced with "clock-freq-min-max". Minimum clock value might be set to 100K by default. Then MMC core should try to find the correct value from 400K to 100K. So it just needs to set Maximum clock value. Signed-off-by:
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Jaehoon Chung authored
Remove the unnecessary mmc_data structure. Instead, cmd->data can be used. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Reviewed-by:
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Jaehoon Chung authored
This patch removed the meaningless value. Instead, use the cookie's enum values for executing correctly. Signed-off-by:
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Jaehoon Chung authored
stop_cmdr should be set to values relevant to stop command. It migth be assigned to values whatever there is mrq->stop or not. Then it doesn't need to use dw_mci_prepare_command(). It's enough to use the prep_stop_abort for preparing stop command. Signed-off-by:
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Jaehoon Chung authored
If DW_MMC_CARD_NO_USE_HOLD isn't set, it's usesd by default. Enve if SDMMC_CMD_USB_HOLD_REG is set in prepare_command(), but it doesn't set in pre_stop_abort(). To maintain the consistency, add the checking condition for this. Signed-off-by:
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Jaehoon Chung authored
If there is no property "clock-freq-min-max", mmc->f_min should be set to 400K by default. But Some SoC can be used 100K. When 100K is used, MMC core will try to check from 400K to 100K. Reported-by:
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Jaehoon Chung authored
If display the debug message, this message should be spamming. If flags is maintained the previous value, didn't display the debug message. Signed-off-by:
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Jaehoon Chung authored
Developer wants to see the real register value, not register offset. This patch fixed to display the real value of register. Signed-off-by:
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Colin Ian King authored
Trivial fix to spelling mistake "desciptor" to "descriptor" in dev_dbg message. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Linus Walleij authored
By moving the mmc_packed_init() and mmc_packed_clean() into the only file in the kernel where they are used, we save two exported functions and can staticize those to the block.c file. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Linus Walleij authored
The struct mmc_blk_request contains an opaque void *data that is actually only used to store a pointer to a per-request struct mmc_blk_data. This is confusing, so rename the member to blkdata and forward-declare the block.c local struct. Signed-off-by:
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Linus Walleij authored
Instead of open coding the check for the same thing that the helper checks: use the helper. Signed-off-by:
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ahaslam@baylibre.com authored
Request card detect and write protect gpios using the provided API by mmc core. If a gpio is provided for card detect, we don't need to poll. So only use polling when a gpio is not provided. Once all pdata users register the gpios using gpio descriptors, we could remove the platform callbacks. Signed-off-by:
Axel Haslam <ahaslam@baylibre.com> Signed-off-by:
David Lechner <david@lechnology.com>
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ahaslam@baylibre.com authored
Card detect and write protect are currently not working on a DT boot, and the driver relies on polling to get the state of the card. The current code depends on platform data callbacks to register and get the state of the gpios. mmc core provides a generic way to parse device tree configuration, which will take care of registering the gpios for us, lets use it so that we don't need to poll, and parse the same properties. Signed-off-by:
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Wolfram Sang authored
We surely have SDIO support by now :) Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Wolfram Sang authored
Commit 7729c7a2 ("mmc: tmio: Provide separate interrupt handlers") refactored the sdio irq handler and wrongly used the mask for SD irqs, not for SDIO irqs. This doesn't really matter in practice because both values keep the only interrupt we are interested in. But still, this is wrong and wants to be fixed. Signed-off-by:
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Alexey Khoroshilov authored
wbsd_request_dma() does not check for dma mapping errors. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by:
Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by:
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Dan Carpenter authored
We never set "ret" to RESULT_OK. Fixes: 9f9c4180 ("mmc: mmc_test: add test for non-blocking transfers") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Masahiro Yamada authored
The type of host->private is (unsigned long *). No cast is needed to return an opaque pointer. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
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Scott Branden authored
Add bytewise register accesses support for newer versions of IPROC SDHCI controllers. Previous sdhci-iproc versions of SDIO controllers (such as Raspberry Pi and Cygnus) only allowed for 32-bit register accesses. Signed-off-by:
Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by:
Scott Branden <scott.branden@broadcom.com> Acked-by:
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Scott Branden authored
Adds brcm,sdhci-iproc compat string to DT bindings document for the iProc SDHCI driver. Signed-off-by:
Anup Patel <anup.patel@broadcom.com> Signed-off-by:
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Simon Horman authored
Add tuning support for use with SDR104 mode This includes adding support for the sampling clock controller (SCC). Based on work by Ai Kyuse. Cc: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by:
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Ai Kyuse authored
Add tuning support for use with SDR104 mode Signed-off-by:
Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by:
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Ai Kyuse authored
Add hw reset support. Signed-off-by:
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Simon Horman authored
Signed-off-by:
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Ai Kyuse authored
An illegal sequence command error may occur if there is a stopbit or cmd_index error as well as a CRC error. The correct course of action is to re-enable IRQs An illegal sequence data error may occur if there is a CRC or stopbit error, or underrun. In this case set data->error correctly. This is in preparation for enabling tuning support which relies on differentiating between illegal sequence and other errors. Signed-off-by:
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Simon Horman authored
This is in preparation for restoring saved tuning parameters when resuming the TMIO driver. Signed-off-by:
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