ARM64: hisi: SoC driver updates for 5.1

- Add compatibility support for different FWs in the hisi LPC bus driver

* tag 'hisi-drivers-for-5.1' of git://github.com/hisilicon/linux-hisi:
  bus: hisi_lpc: Don't fail probe for unrecognised child devices
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

clk: tegra: Changes for v5.1-rc1

This contains a couple of prerequisite patches to enable CPU frequency
scaling on Tegra210.

* tag 'tegra-for-5.1-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
  clk: tegra: dfll: add CVB tables for Tegra210
  clk: tegra: dfll: round down voltages based on alignment
  clk: tegra: dfll: support PWM regulator control
  clk: tegra: dfll: CVB calculation alignment with the regulator
  clk: tegra: dfll: registration for multiple SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

cpufreq: tegra: Add support for Tegra210

This uses the DFLL clock support to enable CPU frequency scaling on
Tegra210.

* tag 'tegra-for-5.1-cpufreq' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  cpufreq: dt-platdev: add Tegra210 to blacklist
  cpufreq: tegra124: extend to support Tegra210
  cpufreq: tegra124: do not handle the CPU rail
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-5.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

soc/tegra: Changes for v5.1-rc1

This contains a couple of miscellaneous fixes for minor issues and a
largish rework of the PMC driver to make it work on systems where the
PMC has been locked down and can only be accessed from secure firmware.

* tag 'tegra-for-5.1-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: pmc: Support systems where PMC is marked secure
  soc/tegra: pmc: Explicitly initialize all fields
  soc/tegra: pmc: Make alignment consistent
  soc/tegra: pmc: Pass struct tegra_pmc * where possible
  soc/tegra: pmc: Make tegra_powergate_is_powered() a local function
  soc/tegra: pmc: Add missing kerneldoc
  soc/tegra: pmc: Sort includes alphabetically
  soc/tegra: pmc: Use TEGRA186_ prefix for GPIO names
  soc/tegra: fuse: Fix typo in tegra210_init_speedo_data
  soc/tegra: fuse: Fix illegal free of IO base address
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-5.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

firmware: tegra: Changes for v5.1-rc1

These changes add support for BPMP on Tegra210.

* tag 'tegra-for-5.1-firmware' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  firmware/tegra: Enable Tegra186 BPMP support on Tegra194
  firmware: tegra: Conditionally support SoC generations
  firmware: tegra: bpmp-tegra186: Remove unused includes
  firmware: tegra: add bpmp driver for Tegra210
  firmware: tegra: Refactor BPMP driver
  firmware: tegra: Reword messaging terminology
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Reset controller changes for v5.1

This adds the include/linux/reset directory to MAINTAINERS for reset
specific headers and adds headers for sunxi and socfpga in there to
get rid of a few extern function declarations.
There is a new reset driver for the Broadcom STB reset controller and
the i.MX7 system reset controller driver is extended to support i.MX8MQ
as well. Finally, there is a new header with reset id constants for
the Meson G12A SoC, which has a reset controller identical to Meson AXG
and thus can reuse its driver and DT bindings.

* tag 'reset-for-5.1' of git://git.pengutronix.de/git/pza/linux:
  dt-bindings: reset: meson: add g12a bindings
  reset: imx7: Add support for i.MX8MQ IP block variant
  reset: imx7: Add plubming to support multiple IP variants
  reset: Add Broadcom STB SW_INIT reset controller driver
  dt-bindings: reset: Add document for Broadcom STB reset controller
  reset: socfpga: declare socfpga_reset_init in a header file
  reset: sunxi: declare sun6i_reset_init in a header file
  MAINTAINERS: use include/linux/reset for reset controller related headers
  dt-bindings: reset: imx7: Document usage on i.MX8MQ SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/drivers

Amlogic: driver updates for v5.1
- clock measure: add support for G12a SoC family
- misc. fixes

* tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  soc: amlogic: clk-measure: add axg and g12a support
  dt-bindings: amlogic: add new compatible devices to clk_measure
  soc: amlogic: canvas: Fix meson_canvas_get when probe failed
  soc: amlogic: add missing of_node_put()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers

i.MX drivers update for 5.1:
 - Do not get GPCv2 driver depend on SOC_IMX8MQ since the driver is
   going to be used on more SoCs than just i.MX8MQ.
 - Add power domain information into SCU bindings document.
 - Add support of start/stop a CPU into imx firmware driver.
 - Support multiple address ranges per child node for imx-weim bus
   driver.

* tag 'imx-drivers-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  firmware: imx: Add support to start/stop a CPU
  soc: imx: Break dependency on SOC_IMX8MQ for GPCv2
  firmware: imx: scu-pd: add fallback compatible string support
  dt-bindings: fsl: scu: add imx8qm scu power domain support
  dt-bindings: fsl: scu: add fallback compatible string for power domain
  bus: imx-weim: guard against timing configuration conflicts
  bus: imx-weim: support multiple address ranges per child node
  dt-bindings: bus: imx-weim: document multiple address ranges per child node
  soc: imx: gpcv2: handle reset clocks
  soc: imx: gpcv2: handle additional power-down bits in handshake register
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arm64: zynqmp: SoC changes for v5.1

- Extend firmware interface with reset, nvmem,
  power management and power domain support

- Add reset, nvmem driver, power management and
  power domain drivers
-

* tag 'zynqmp-soc-for-v5.1' of https://github.com/Xilinx/linux-xlnx:
  drivers: soc: xilinx: Add ZynqMP power domain driver
  firmware: xilinx: Add APIs to control node status/power
  dt-bindings: power: Add ZynqMP power domain bindings
  drivers: soc: xilinx: Add ZynqMP PM driver
  firmware: xilinx: Implement ZynqMP power management APIs
  dt-bindings: soc: Add ZynqMP PM bindings
  nvmem: zynqmp: Added zynqmp nvmem firmware driver
  dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
  firmware: xilinx: Add zynqmp_pm_get_chipid() API
  reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.
  dt-bindings: reset: Add bindings for ZynqMP reset driver
  firmware: xilinx: Add reset API's
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The zynqmp-genpd driver communicates the usage requirements
for logical power domains / devices to the platform FW.
FW is responsible for choosing appropriate power states,
taking Linux' usage information into account.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add Xilinx ZynqMP firmware APIs to control node status
and power. These APIs allows turning on/off power domain
and setting capabilities of devices present in power domain.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add ZynqMP PM driver. PM driver provides power management
support for ZynqMP.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add Xilinx ZynqMP firmware APIs to set suspend mode
and inform firmware that master has initialized its
own power management.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

This is done via RPC call to SCU.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add device tree bindings for the reset controller of g12a SoC family.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

Currently for ACPI-based FW we fail the probe for an unrecognised child
HID.

However, there is FW in the field with LPC child devices having fake HIDs,
namely "IPI0002", which was an IPMI device invented to support the
initial out-of-tree LPC host driver, different from the final mainline
version.

To provide compatibility support for these dodgy FWs, just discard the
unrecognised HIDs instead of failing the probe altogether.
Tested-by: Zengruan Ye <yezengruan@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

Add support for the axg and g12a SoC family in amlogic clk measure
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[khilman: squashed some fixups from Martin]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Add the axg and g12a SoC family compatible to the clock measure bindings
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

When probe fails, a platforn_device is still associated to the node,
but dev_get_drvdata() returns NULL.

Handle this case by returning a consistent error.

Fixes: d4983983 ("soc: amlogic: add meson-canvas driver")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Maxime Jourdan <mjourdan@baylibre.com>
[khilman: fixed minor typo in comment ]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

The BPMP implementation on Tegra194 is mostly compatible with the
implementation on Tegra186, so make sure the latter is available when
support for Tegra194 is enabled.
Suggested-by: Timo Alho <talho@nvidia.com>
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Only include support for Tegra210 and Tegra186 in the BPMP driver if
support for those SoCs was selected. This fixes a build failure seen
on 32-bit ARM allmodconfig builds, but could also happen on 64-bit
ARM builds if either Tegra210 or Tegra186 were not selected.
Reported-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Timo Alho <talho@nvidia.com>
Tested-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The call to of_parse_phandle returns a node pointer with refcount
incremented thus it must be explicitly decremented here after the last
usage.
Signed-off-by: Wen Yang <yellowriver2010@hotmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Fixes: d4983983 ("soc: amlogic: add meson-canvas driver")
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

Tegra210 uses "tegra124-cpufreq" platform driver to register device data
for "cpufreq-dt" driver. So add it in the blacklist for
"cpufreq-dt-platdev" driver to drop that.

Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra210 uses the same methodology as Tegra124 for CPUFreq controlling
that based on DFLL clock. So extending this driver to support Tegra210.

Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The Tegra124 cpufreq driver has no information to handle the Vdd-CPU
rail. So this driver shouldn't handle for the CPU clock switching from
DFLL to other PLL clocks. It was designed to work on DFLL clock only,
which handle the frequency/voltage scaling in the background.

This patch removes the driver dependency of the CPU rail, as well as not
allow it to be built as a module and remove the removal function. So it
can keep working on DFLL clock.

Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Tegra210 has a DFLL as well and can share the majority of the code with
the Tegra124 implementation. So build the same code for both platforms.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add CVB tables with different chip characterization, so that we can
generate the customize OPP table that suitable for different chips with
different SKUs.

The parameter 'tune_high_min_millivolts' is first time introduced in
this patch, which didn't use in the DFLL driver for clock and voltage
tuning before. It will be used later when DFLL in high voltage range.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

When generating the OPP table, the voltages are round down with the
alignment from the regulator. The alignment should be applied for
voltages look up as well.

Based on the work of Penny Chiu <pchiu@nvidia.com>.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The DFLL hardware supports two modes (I2C and PWM) for voltage control
when requesting a frequency. In this patch, we introduce PWM mode support.

To support that, we re-organize the LUT for unifying the table for both
cases of I2C and PWM mode. And generate that based on regulator info.
For the PWM-based regulator, we get this info from DT. And do the same as
the case of I2C LUT, which can help to map the PMIC voltage ID and voltages
that the regulator supported.

The other parts are the support code for initializing the DFLL hardware
to support PWM mode. Also, the register debugfs file is slightly
reworked to only show the i2c registers when I2C mode is in use.

Based on the work of Peter De Schrijver <pdeschrijver@nvidia.com>.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The CVB table contains calibration data for the CPU DFLL based on
process characterization. The regulator step and offset parameters depend
on the regulator supplying vdd-cpu, not on the specific Tegra SKU.

When using a PWM controlled regulator, the voltage step and offset are
determined by the regulator type in use. This is specified in DT. When
using an I2C controlled regulator, we can retrieve them from CPU regulator
Then pass this information to the CVB table calculation function.

Based on the work done of "Peter De Schrijver <pdeschrijver@nvidia.com>"
and "Alex Frid <afrid@nvidia.com>".
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

In a future patch, support for the DFLL in Tegra210 will be introduced.
This requires support for more than 1 set of CVB and CPU max frequency
tables.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

This patch adds zynqmp nvmem firmware driver to access the
SoC revision information from the hardware register.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

This patch adds a new API to provide access to the
hardware related data like soc revision, IDCODE... etc.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Merge tag 'soc-fsl-next-v5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers

NXP/FSL SoC driver updates for v5.1

DPIO driver
- Clean up the remove path in the dpio driver so that successive
  bind/unbind commands behave properly
- Add the ability to automatically create a device link between a
  consumer device on the fsl-mc bus and a supplier one
- Add prefetch to dpio dequeue to improve performance
- Update the type of dpio APIs to align with buffer pool id register
  field

guts driver
- Prevent allocation failure by reuse the machine type data from device
  tree directly

* tag 'soc-fsl-next-v5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
  soc: fsl: guts: reuse machine name from device tree
  soc: fsl: dpio: Change bpid type to u16
  soc: fsl: dpio: Add prefetch instruction
  bus: fsl-mc: automatically add a device_link on fsl_mc_[portal,object]_allocate
  soc: fsl: dpio: add a device_link at dpaa2_io_service_register
  soc: fsl: dpio: store a backpointer to the device backing the dpaa2_io
  soc: fsl: dpio: keep a per dpio device MC portal
  soc: fsl: dpio: perform DPIO Reset on Probe
  soc: fsl: dpio: use a cpumask to identify which cpus are unused
  soc: fsl: dpio: cleanup the cpu array on dpaa2_io_down
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Add a reset controller driver for Xilinx Zynq UltraScale+ MPSoC.
The zynqmp reset-controller has the ability to reset lines
connected to different blocks and peripheral in the Soc.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add documentation to describe Xilinx ZynqMP reset driver
bindings.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

This Patch Adds reset API's to support release, assert
and status functionalities by using firmware interface.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>