- 30 Apr, 2024 40 commits
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Rodrigo Siqueira authored
Add dcn301_fpu prefix to some of the FPU function with the required adjustments. Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rodrigo Siqueira authored
Add VCO speed parameters in the bounding box array. Acked-by:
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Wayne Lin authored
[Why & How] We accidentally upstream unnecessary files. Remove them. Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This commit just update the code style in two if conditions and in an static array. Acked-by:
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Rodrigo Siqueira authored
This commit add PP_SMU_VER_VG to the pp_smu_ver list. Acked-by:
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Rodrigo Siqueira authored
Add REG_SEQ_SUBMIT and REG_SEQ_WAIT_DONE to optimize the burst write for the regama lut. Acked-by:
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Harry Wentland authored
Some IGT tests fail with the new atomic cursor updates when running on older DCE-based ASICs. To work around these issues keep calling the amdgpu_dm_commit_cursors for each cursor update on DCE, even if those cursor updates coincide with other plane updates. Reviewed-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Tested-by:
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Yang Wang authored
- remove unused callback functions. - make part of mca functions static and refine the function order. Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Harry Wentland authored
Cursors are always programmed independently of updates on other planes. When atomic commits program cursor and surface updates together the cursor update might be locked out by the surface update and not take effect. To combat this program cursor and surface updates together via dc_update_planes_and_stream to ensure they can be applied atomically. When cursor updates come on their own use the old method to program the cursor as dc_update_planes_and_stream isn't handling this case correctly (yet), leading to a flickering screen. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2186Reviewed-by:
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Hawking Zhang authored
v1: Add mmhub v4_1_0 register offset and shift masks header files. (Hawking) v2: Update mmhub v4_1_0 register offset and shift masks header files to RE2. (Likun) v3: Update mmhub v4_1_0 register offset and shift masks header files to RE2.5 (Likun) v4: Clean up mmhub v4_1_0 ip headers (Alex) Signed-off-by:Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Aric Cyr authored
Summary: * Changes across DSC, MST, DMCUB, Panel Replay and misc fixes. * Fixes to cursor programming sequence * Add some missing register defs * Formatting/Sytle fixes Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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Anthony Koo authored
- Adjust the dmub_fw_boot_options reserved bits to be correct Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Likun Gao authored
Add common soc24 ip block. v2: squash in updates (Alex) Signed-off-by:
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Rodrigo Siqueira authored
The string dp_hdmi_dongle_signature_str already uses u8 but the string dp_hdmi_dongle_signature_str does not. Just replace uint8_t with u8 for dp_hdmi_dongle_signature_str. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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Jack Xiao authored
Adjust mes queue initialization before kgq/kcq initialization to enable mes mapping legacy queue. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Jack Xiao authored
Add mes11 map legacy queue packet submission. Signed-off-by:
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Sung Joon Kim authored
[why & how] There are potential issues with Z8 and IPS that need to be addressed and need to add in missing function pointers. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Christian König authored
This reverts drm/amdgpu: fix ftrace event amdgpu_bo_move always move on same heap. The basic problem here is that after the move the old location is simply not available any more. Some fixes were suggested, but essentially we should call the move notification before actually moving things because only this way we have the correct order for DMA-buf and VM move notifications as well. Also rework the statistic handling so that we don't update the eviction counter before the move. v2: add missing NULL check Signed-off-by:
Christian König <christian.koenig@amd.com> Fixes: 94aeb411 ("drm/amdgpu: fix ftrace event amdgpu_bo_move always move on same heap") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3171Reviewed-by:
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Webb Chen authored
[why] VBios & Driver may have differnet pixel rate div policy. If the policy is not same and fast boot is enabled, it would cause the pixel rate is too high after driver only performs stream blank & unblank. [how] We would keep pixel rate div setting by VBios until next mode set. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Webb Chen <yi-lchen@amd.com> Tested-by:
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Cruise authored
[Why] Error correction was enabled in a monitor which doesn't support. [How] Disable error correction if it's not supported Reviewed-by:
Cruise <cruise.hung@amd.com> Tested-by:
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Sung Joon Kim authored
[why & how] The recout x offset was incorrect which led to wrong viewport calculation. For stereo side-by-side case, the slice index should be 0 for both split pipes. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
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Harry Wentland authored
HWSS set_cursor_attributes copies the stream's cursor attributes to the hubp cursor attributes. set_cursor_position might attempt to program the cursor attributes but will program them wrong if they're not set correctly. We need to call HWSS set_cursor_attributes first to ensure hubp has the right attributes to be programmed. Reviewed-by:
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Harry Wentland authored
We're seeing issues when user-space tries to do an atomic update of the primary surface, as well as the cursor. These two updates are separate calls into DC and don't currently act as an atomic update. This might lead to cursor updates being locked out and cursors stuttering. In order to solve this problem we want to separate the setting and programming of cursor attributes and position. That's what we're doing in this patch. The subsequent patch will then be able to use the cursor setters in independent cursor updates, as well as in atomic commits. Reviewed-by:
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Joshua Aberback authored
This reverts commit 0a571e86. [Why] The change being reverted incorrectly assumes that a pointer type was intended, however copying to a new structure is correct. As well, there is no compiler error, it was instead an error in the testing framework being used. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Joshua Aberback <joshua.aberback@amd.com> Tested-by:
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Ilya Bakoulin authored
Not every ASIC implements dp_set_dsc_config. Add condition to prevent calls to unimplemented function. Reviewed-by:
Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] During DP tunnel creation, CM preallocates BW and reduces estimated BW of other DPIA. CM release preallocation only when allocation is complete. Display mode validation logic validates timings based on bw available per host router. In multi display setup, this causes bw allocation failure when allocation greater than estimated bw. [How] Do zero alloc to make the CM to release preallocation and update estimated BW correctly for all DPIAs per host router. Reviewed-by:
PeiChen Huang <peichen.huang@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Hersen Wu authored
[Why] DSC debugfs, such as dp_dsc_clock_en_read, use aconnector->dc_link to find pipe_ctx for display. Displays connected to MST hub share the same dc_link. DSC instance is from pipe_ctx. This causes incorrect DSC instance for display connected to MST hub. [How] Add aconnector->sink check to find pipe_ctx. CC: stable@vger.kernel.org Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Tested-by:
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Hawking Zhang authored
Add initial soc24 support. v1: Add soc24 common ip block. v2: Switch to new select_se_sh/enter_safe_mode interface. v3: squash in correct ext rev id, etc. (Alex) Signed-off-by: -
Nicholas Kazlauskas authored
[Why] It's possible that the write hasn't fully completed by the time we send (and flush) a command to DMCUB to notify idle to request IPS2 exit. [How] Perform a readback of the volatile structure into dc_dmub_srv state. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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Ethan Bitnun authored
[Description] - Block FPO if the max stretch refresh rate is low enough to cause a flicker by storing the maximum safe refresh decrease from nominal in stream. - Brought over various Freesync Luminance functions to dc. Use these new functions to block fpo if we will flicker. - Generalized increase/reduce dependent functions to reduce code clutter and allow for easier use. - Added a debug option to enable the feature. Disabled by default. Co-authored-by:
Ethan Bitnun <etbitnun@amd.com> Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Hawking Zhang authored
Add enum definitions for soc24. v2: Updates (Alex) v3: Updates (Alex) v4: Fix clash with display code (Alex) Signed-off-by:
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Hawking Zhang authored
v1: Add gc v12_0_0 register offset and shift masks header files. (Hawking) v2: Update gc v12_0_0 register offset and shift masks header files to LSD version. (Likun) v3: Update gc v12_0_0 register offset and shift masks header files to RE3 version. (Likun) v4: Updates (Alex) v5: updates (Alex) Signed-off-by: -
George Shen authored
[Why] Upon disconnecting a UHBR SST display, the disconnection and the SetTimings to disable the display can occur such that link_set_dpms_off occurs after the disconnection has already processed (link->type is dc_connection_none). Thus, the AUX related operations should be skipped when clearing the payload allocation table. Reviewed-by:
George Shen <george.shen@amd.com> Tested-by:
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Gabe Teeger authored
New request from KMD/VBIOS in order to support new UMA carveout model. This fixes a null dereference from accessing Ctx->dc_bios->integrated_info while it was NULL. DAL parses through the BIOS and extracts the necessary integrated_info but was missing a case for the new BIOS version 2.3. Reviewed-by:
Gabe Teeger <gabe.teeger@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Avoid race condition which puts LTTPR into bad state during UHBR LT. [HOW] Delay 30ms between starting UHBR TPS1 PHY output and sending TPS1 via DPCD. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Sung-huai Wang authored
[Why] TCON data is corrupted after electro static discharge test. Once the TCON data get corrupted, they will get themselves reset and send HPD_IRQ to source side. [How] Support HPD_IRQ for internal link, and restore the PSR/Replay setup. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Sung-huai Wang <danny.wang@amd.com> Tested-by:
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Sung Joon Kim authored
[why & how] Need to update the function pointers that perform the power up and down sequence to reuse the modified sequence as a requirement. Reviewed-by:
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Swapnil Patel authored
[Why & How] Currently DCN315 clk manager is missing code to enable/disable dtbclk. Because of this, "optimized_required" flag is constantly set and this prevents FreeSync from engaging for certain high bandwidth display Modes which require DTBCLK. Reviewed-by:
Swapnil Patel <swapnil.patel@amd.com> Tested-by:
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Natanel Roizenman authored
[WHY] When switching from "Extend" to "Second Display Only" we sometimes call resource_get_otg_master_for_stream on a stream for the eDP, which is disconnected. This leads to a null pointer dereference. [HOW] Added a null check in dc_resource.c/resource_log_pipe_topology_update. CC: stable@vger.kernel.org Reviewed-by:
Natanel Roizenman <natanel.roizenman@amd.com> Tested-by:
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Dennis Chan authored
When PHY power off, the DP_SEC_CNTL cannot be configured and cause disable Adaptive sync SDP failed. Regarding the issue, the driver will disabled AS-SDP in replay state machine. Reviewed-by:
ChunTao Tso <chuntao.tso@amd.com> Acked-by:
Dennis Chan <dennis.chan@amd.com> Tested-by:
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