- 20 Oct, 2023 3 commits
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Dave Airlie authored
Merge tag 'mediatek-drm-next-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 6.7 1. Add support MT8188 dsi function 2. Fix coverity issue with unintentional integer overflow 3. Add support MT8188 dp/edp function 4. Fix memory leak on ->get_edid callback audio detection and error path. 5. Add connector dynamic selection capability 6. MediaTek DDP GAMMA - 12-bit LUT support 7. mtk_dsi: Fix NO_EOT_PACKET settings/handling [airlied: add bitfield.h include] Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231018135846.5811-1-chunkuang.hu@kernel.org
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2023-10-19' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Driver Changes: Fixes/improvements/new stuff: - Retry gtt fault when out of fence registers (Ville Syrjälä) - Determine context valid in OA reports [perf] (Umesh Nerlige Ramappa) Future platform enablement: - GuC based TLB invalidation for Meteorlake (Jonathan Cavitt, Prathap Kumar Valsan) - Don't set PIPE_CONTROL_FLUSH_L3 [mtl] (Vinay Belgaumkar) Miscellaneous: - Clean up zero initializers [guc,pxp] (Ville Syrjälä) - Prevent potential null-ptr-deref in engine_init_common (Nirmoy Das) Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
- Add new DG2 PCI IDs (Shekhar) - Remove watchdog timers for PSR on Lunar Lake (Mika Kahola) - DSB changes for proper handling of LUT programming (Ville) - Store DSC DPCD capabilities in the connector (Imre) - Clean up zero initializers (Ville) - Remove Meteor Lake force_probe protection (RK) Signed-off-by:
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- 18 Oct, 2023 13 commits
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Umesh Nerlige Ramappa authored
When supporting OA for TGL, it was seen that the context valid bit in the report ID was not defined, however revisiting the spec seems to have this bit defined. The bit is used to determine if a context is valid on a context switch and is essential to determine active and idle periods for a context. Re-enable the context valid bit for gen12 platforms. BSpec: 52196 (description of report_id) v2: Include BSpec reference (Ashutosh) Fixes: 00a7f0d7 ("drm/i915/tgl: Add perf support on TGL") Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230802202854.1224547-1-umesh.nerlige.ramappa@intel.com
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Vinay Belgaumkar authored
This bit does not cause an explicit L3 flush. We already use PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose. v2: Use FLUSH_L3 only pre-MTL since spec will likely remain the same going forward. Cc: Nirmoy Das <nirmoy.das@intel.com> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Acked-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
Nirmoy Das <nirmoy.das@intel.com> Signed-off-by:
Vinay Belgaumkar <vinay.belgaumkar@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by:
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AngeloGioacchino Del Regno authored
Due to the initial confusion about MIPI_DSI_MODE_EOT_PACKET, properly renamed to MIPI_DSI_MODE_NO_EOT_PACKET, reflecting its actual meaning, both the DSI_TXRX_CON register setting for bit (HSTX_)DIS_EOT and the later calculation for horizontal sync-active (HSA), back (HBP) and front (HFP) porches got incorrect due to the logic being inverted. This means that a number of settings were wrong because....: - DSI_TXRX_CON register setting: bit (HSTX_)DIS_EOT should be set in order to disable the End of Transmission packet; - Horizontal Sync and Back/Front porches: The delta used to calculate all of HSA, HBP and HFP should account for the additional EOT packet. Before this change... - Bit (HSTX_)DIS_EOT was being set when EOT packet was enabled; - For HSA/HBP/HFP delta... all three were wrong, as words were added when EOT disabled, instead of when EOT packet enabled! Invert the logic around flag MIPI_DSI_MODE_NO_EOT_PACKET in the MediaTek DSI driver to fix the aforementioned issues. Fixes: 8b2b99fd ("drm/mediatek: dsi: Fine tune the line time caused by EOTp") Fixes: c87d1c4b ("drm/mediatek: dsi: Use symbolized register definition") Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Alexandre Mergnat <amergnat@baylibre.com> Tested-by:
Michael Walle <mwalle@kernel.org> Link: https://patchwork.kernel.org/project/dri-devel/patch/20230523104234.7849-1-angelogioacchino.delregno@collabora.com/Signed-off-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org>
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Nirmoy Das authored
If measure_breadcrumb_dw() returns an error and bce isn't created, this commit ensures that intel_engine_destroy_pinned_context() is not called with a NULL bce. v2: Fix the subject s/UAF/null-ptr-deref(Jani) Fixes: b3527499 ("drm/i915: Create a kernel context for GGTT updates") Cc: Oak Zeng <oak.zeng@intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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https://gitlab.freedesktop.org/agd5f/linuxDave Airlie authored
amd-drm-next-6.7-2023-10-13: amdgpu: - DC replay fixes - Misc code cleanups and spelling fixes - Documentation updates - RAS EEPROM Updates - FRU EEPROM Updates - IP discovery updates - SR-IOV fixes - RAS updates - DC PQ fixes - SMU 13.0.6 updates - GC 11.5 Support - NBIO 7.11 Support - GMC 11 Updates - Reset fixes - SMU 11.5 Updates - SMU 13.0 OD support - Use flexible arrays for bo list handling - W=1 Fixes - SubVP fixes - DPIA fixes - DCN 3.5 Support - Devcoredump fixes - VPE 6.1 support - VCN 4.0 Updates - S/G display fixes - DML fixes - DML2 Support - MST fixes - VRR fixes - Enable seamless boot in more cases - Enable content type property for HDMI - OLED fixes - Rework and clean up GPUVM TLB flushing - DC ODM fixes - DP 2.x fixes - AGP aperture fixes - SDMA firmware loading cleanups - Cyan Skillfish GPU clock counter fix - GC 11 GART fix - Cache GPU fault info for userspace queries - DC cursor check fixes - eDP fixes - DC FP handling fixes - Variable sized array fixes - SMU 13.0.x fixes - IB start and size alignment fixes for VCN - SMU 14 Support - Suspend and resume sequence rework - vkms fix amdkfd: - GC 11 fixes - GC 10 fixes - Doorbell fixes - CWSR fixes - SVM fixes - Clean up GC info enumeration - Rework memory limit handling - Coherent memory handling fixes - Use partial migrations in GPU faults - TLB flush fixes - DMA unmap fixes - GC 9.4.3 fixes - SQ interrupt fix - GTT mapping fix - GC 11.5 Support radeon: - Misc code cleanups - W=1 Fixes - Fix possible buffer overflow - Fix possible NULL pointer dereference UAPI: - Add EXT_COHERENT memory allocation flags. These allow for system scope atomics. Proposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88 - Add support for new VPE engine. This is a memory to memory copy engine with advanced scaling, CSC, and color management features Proposed mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713 - Add INFO IOCTL interface to query GPU faults Proposed Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238 Proposed libdrm MR: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/298Signed-off-by:
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Radhakrishna Sripada authored
Meteor Lake has demonstrated consistent stability for some time. All user-space API modifications tide to its core platform functions are operational. The necessary firmware components are set up and comprehensive testing has been condused over a period. Given the recent faborable CI results, as well, we believe it's time to eliminate the 'force_probe' prerequisite and activate the platform by default. Signed-off-by:
Aditya Chauhan <aditya.chauhan@intel.com> Signed-off-by:
Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by:
Chris Wilson <chris.p.wilson@linux.intel.com> Signed-off-by:
Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Signed-off-by:
Jonathan Cavitt <jonathan.cavitt@intel.com> Signed-off-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
Lee Shawn C <shawn.c.lee@intel.com> Tested-by:
Karthik B S <karthik.b.s@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231008164824.919262-1-andi.shyti@linux.intel.com
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Jonathan Cavitt authored
Enable GuC TLB invalidations for MTL. Though more platforms than just MTL support GuC TLB invalidations, MTL is presently the only platform that requires it for any purpose, so only enable it there for now to minimize cross-platform impact. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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Jonathan Cavitt authored
For the gt_tlb live selftest, when operating on the GSC engine, increase the timeout from 10 ms to 200 ms because the GSC engine is a bit slower than the rest. Signed-off-by:
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Jonathan Cavitt authored
It is not an error for GuC TLB invalidations to fail when the GT is wedged or disabled, so do not process a wait failure as one in guc_send_invalidate_tlb. Signed-off-by:
Fei Yang <fei.yang@intel.com> Signed-off-by:
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Jonathan Cavitt authored
In case of GT is suspended, don't allow submission of new TLB invalidation request and cancel all pending requests. The TLB entries will be invalidated either during GuC reload or on system resume. Signed-off-by:
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Prathap Kumar Valsan authored
The GuC firmware had defined the interface for Translation Look-Aside Buffer (TLB) invalidation. We should use this interface when invalidating the engine and GuC TLBs. Add additional functionality to intel_gt_invalidate_tlb, invalidating the GuC TLBs and falling back to GT invalidation when the GuC is disabled. The invalidation is done by sending a request directly to the GuC tlb_lookup that invalidates the table. The invalidation is submitted as a wait request and is performed in the CT event handler. This means we cannot perform this TLB invalidation path if the CT is not enabled. If the request isn't fulfilled in two seconds, this would constitute an error in the invalidation as that would constitute either a lost request or a severe GuC overload. With this new invalidation routine, we can perform GuC-based GGTT invalidations. GuC-based GGTT invalidation is incompatible with MMIO invalidation so we should not perform MMIO invalidation when GuC-based GGTT invalidation is expected. The additional complexity incurred in this patch will be necessary for range-based tlb invalidations, which will be platformed in the future. Signed-off-by:
Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Signed-off-by:
Bruce Chang <yu.bruce.chang@intel.com> Signed-off-by:
Chris Wilson <chris.p.wilson@intel.com> Signed-off-by:
Aravind Iddamsetty <aravind.iddamsetty@intel.com> Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Signed-off-by:
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Jonathan Cavitt authored
As of now, there is no mechanism for tracking a given request's progress through the queue. Instead, add a helper that returns an estimated maximum time the queue should take to drain if completely full. Suggested-by:
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Jonathan Cavitt authored
Add device info flags for if GuC TLB Invalidation is enabled. Signed-off-by:
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- 17 Oct, 2023 4 commits
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Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231012122442.15718-6-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: -
Dave Airlie authored
Merge tag 'drm-habanalabs-next-2023-10-10' of https://git.kernel.org/pub/scm/linux/kernel/git/ogabbay/linux into drm-next This tag contains habanalabs driver changes for v6.7. The notable changes are: - uAPI changes: - Expose tsc clock sampling to better sync clock information in profiler. - Enhance engine error reporting in the info ioctl. - Block access to the eventfd operations through the control device. - Disable the option of the user to register multiple times with the same offset for timestamp dump by the driver. If a user wants to use the same offset in the timestamp buffer for different interrupt, it needs to first de-register the offset. - When exporting dma-buf (for p2p), force the user to specify size/offset in multiples of PAGE_SIZE. This is instead of the driver doing the rounding to PAGE_SIZE, which has caused the driver to map more memory than was intended by the user. - New features and improvements: - Complete the move of the driver to the accel subsystem by removing the custom habanalabs class and major and registering to accel subsystem. - Move the firmware interface files to include/linux/habanalabs. This is a pre-requisite for upstreaming the NIC drivers of Gaudi (as they need to include those files). - Perform device hard-reset upon PCIe AXI drain event to prevent the failure from cascading to different IP blocks in the SoC. In secured environments, this is done automatically by the firmware. - Print device name when it is removed for better debuggability. - Add support for trace of dma map sgtable operations. - Optimize handling of user interrupts by splitting the interrupts to two lists. One list for fast handling and second list for handling with timestamp recording, which is slower. - Prevent double device hard-reset due to 2 adjacent H/W events. - Set device status 'malfunction' while in rmmod. - Firmware related fixes: - Extend preboot timeout because preboot loading might take longer than expected in certain cases. - Add a protection mechanism for the Event Queue. In case it is full, the firmware will be able to notify about it through a dedicated interrupt. - Perform device hard-reset in case scrubbing of memory has failed. - Bug fixes and code cleanups: - Small fixes of dma-buf handling in Gaudi2, such as handling an offset != 0, using the correct exported size, creation of sg table. - Fix spmu mask creation. - Fix bug in wait for cs completion for decoder workloads. - Cleanup Greco name from documentation. - Fix bug in recording timestamp during cs completion interrupt handling. - Fix CoreSight ETF configuration and flush logic. - Fix small bug in hpriv_list handling (the list that contains the private data per process that opens our device). Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-intel-gt-next-2023-10-12' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Driver Changes: Fixes/improvements/new stuff: - Register engines early to avoid type confusion (Mathias Krause) - Suppress 'ignoring reset notification' message [guc] (John Harrison) - Update 'recommended' version to 70.12.1 for DG2/ADL-S/ADL-P/MTL [guc] (John Harrison) - Enable WA 14018913170 [guc, dg2] (Daniele Ceraolo Spurio) Future platform enablement: - Clean steer semaphore on resume (Nirmoy Das) - Skip MCR ops for ring fault register [mtl] (Nirmoy Das) - Make i915_gem_shrinker multi-gt aware [gem] (Jonathan Cavitt) - Enable GGTT updates with binder in MTL (Nirmoy Das, Chris Wilson) - Invalidate the TLBs on each GT (Chris Wilson) Miscellaneous: - Clarify type evolution of uabi_node/uabi_engines (Mathias Krause) - Annotate struct ct_incoming_msg with __counted_by [guc] (Kees Cook) - More use of GT specific print helpers [gt] (John Harrison) Signed-off-by:
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- 16 Oct, 2023 20 commits
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Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: -
Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: -
Ville Syrjälä authored
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: -
Ville Syrjälä authored
If we can't find a free fence register to handle a fault in the GMADR range just return VM_FAULT_NOPAGE without populating the PTE so that userspace will retry the access and trigger another fault. Eventually we should find a free fence and the fault will get properly handled. A further improvement idea might be to reserve a fence (or one per CPU?) for the express purpose of handling faults without having to retry. But that would require some additional work. Looks like this may have gotten broken originally by commit 39965b37 ("drm/i915: don't trash the gtt when running out of fences") as that changed the errno to -EDEADLK which wasn't handle by the gtt fault code either. But later in commit 2feeb528 ("drm/i915/gt: Fix -EDEADLK handling regression") I changed it again to -ENOBUFS as -EDEADLK was now getting used for the ww mutex dance. So this fix only makes sense after that last commit. Cc: stable@vger.kernel.org Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9479 Fixes: 2feeb528 ("drm/i915/gt: Fix -EDEADLK handling regression") Signed-off-by:
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AngeloGioacchino Del Regno authored
Compress the entry for mediatek,mt8173-disp-aal, as it fits in one line, and fix the style; while at it, also add the usual sentinel comment to the last entry. This commit brings no functional changes. Reviewed-by:
CK Hu <ck.hu@mediatek.com> Signed-off-by:
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AngeloGioacchino Del Regno authored
The mtk_disp_gamma structure was completely undocumented: add some kerneldoc documentation to it. Reviewed-by:
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AngeloGioacchino Del Regno authored
The kerneldoc for struct mtk_disp_aal is missing: write one and document this structure. Reviewed-by:
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AngeloGioacchino Del Regno authored
All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Reviewed-by:
Jason-JH.Lin <jason-jh.lin@mediatek.com> Reviewed-by:
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AngeloGioacchino Del Regno authored
Disable relay mode at the end of LUT programming to make sure that the processed image goes through in both DISP_GAMMA and DISP_AAL for gamma setting. Reviewed-by:
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AngeloGioacchino Del Regno authored
Now that this driver supports 12-bit LUTs, we can add support for the DISP_GAMMA found on the MT8195 SoC: add its driver data and compatible. Signed-off-by:
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AngeloGioacchino Del Regno authored
New SoCs, like MT8195, not only may support bigger lookup tables, but have got a different register layout to support bigger precision: support specifying the number of `lut_bits` for each SoC and use it in mtk_gamma_set_common() to perform the right calculations and add support for 12-bit gamma lookup tables. While at it, also reorder the variables in mtk_gamma_set_common() and rename `lut_base` to `lut0_base` to improve readability. Reviewed-by:
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AngeloGioacchino Del Regno authored
Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by:
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AngeloGioacchino Del Regno authored
In preparation for adding a 12-bits gamma support for the DISP_GAMMA IP, remove the mtk_gamma_set_common() function and move the relevant bits in mtk_gamma_set() for DISP_GAMMA and mtk_aal_gamma_set() for DISP_AAL: since the latter has no more support for gamma manipulation (being moved to a different IP) in newer revisions, those functions are about to diverge and it makes no sense to keep a common one (with all the complications of passing common data and making exclusions for device driver data) for just a few bits. This commit brings no functional changes. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by:
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AngeloGioacchino Del Regno authored
Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. Reviewed-by:
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AngeloGioacchino Del Regno authored
Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. Reviewed-by:
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AngeloGioacchino Del Regno authored
Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Note: GAMMA should get enabled in between vblanks, but this requires many efforts in order to make this happen, as that requires migrating all of the writes to make use of CMDQ instead of cpu writes and that's not trivial. For this reason, this patch only moves the LUT enable. The CMDQ rework will come at a later time. Reviewed-by:
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Imre Deak authored
The previous patches converted all users of the DSC DPCD caps to look these up from the connector, so remove the version stored in intel_dp. A follow-up patchset will read out the MST connector specific capabilities in intel_dp_add_mst_connector() -> intel_dp_mst_read_decompression_port_dsc_caps(). v2: - Rebased on intel_edp_get_dsc_sink_cap() addition in the patchset. v3: - Rebased on read-out fix for eDP in the patchset. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> (v1) Reviewed-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231011171606.2540078-3-imre.deak@intel.com
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_mst_mode_valid_ctx(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_config(). Reviewed-by:
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Imre Deak authored
Use the connector's DSC DPCD capabilities in intel_dp_mode_valid(). Reviewed-by:
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