- 19 Mar, 2021 11 commits
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Ville Syrjälä authored
s/intel_/g4x_/ for the externally visible g4x_{dp,hdmi}.c functions. Acked-by:Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210318161015.22070-8-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
Extract the g4x+ HDMI low level code to its own file, leaving intel_hdmi.c to deal with higher level issues. The infoframe support I decided to leave in intel_hdmi.c since I think we need to move that as a whole to its own file. It is after all used also for DP SDPs, so no longer HDMI specific. Acked-by:
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Ville Syrjälä authored
Move the g4x+ DP code into a new file. This will leave mostly platform agnostic code in intel_dp.c. Well, the misplaced phy test stuff pretty much ruins that, but let's squint real hard for now. v2: Add comment exlaining which platforms are covered (Daniel) Leave intel_dp_unused_lane_mask() be since it is pretty generic Acked-by: -
Ville Syrjälä authored
Most of intel_dp_encoder_reset() is for pre-ddi platforms. Make a clean split. Reviewed-by:
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Ville Syrjälä authored
intel_dp_program_link_training_pattern() clearly belongs in intel_dp_link_training.c. Make it so. Reviewed-by:
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Ville Syrjälä authored
If we ever get here with bogus signal levels we've messed up somewhere earlier. Just use MISSING_CASE(). Reviewed-by:
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Ville Syrjälä authored
If we ever get here with TPS3 then intel_dp_training_pattern() is just broken. Replace the careful fallback with just MISSING_CASE(). Reviewed-by:
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Imre Deak authored
By the specification the 0xF0000 - 0xF02FF range is only valid if the LTTPR revision at 0xF0000 is at least 1.4. Disable the LTTPR support otherwise. Fixes: 7b2a4ab8 ("drm/i915: Switch to LTTPR transparent mode link training") Cc: <stable@vger.kernel.org> # v5.11 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Imre Deak authored
By the specification the 0xF0000-0xF02FF range is only valid when the DPCD revision is 1.4 or higher. Disable LTTPR support if this isn't so. Trying to detect LTTPRs returned corrupted values for the above DPCD range at least on a Skylake host with an LG 43UD79-B monitor with a DPCD revision 1.2 connected. v2: Add the actual version check. v3: Fix s/DRPX/DPRX/ typo. Fixes: 7b2a4ab8 ("drm/i915: Switch to LTTPR transparent mode link training") Cc: <stable@vger.kernel.org> # v5.11 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Imre Deak authored
The spec requires to use at least 3.2ms for the AUX timeout period if there are LT-tunable PHY Repeaters on the link (2.11.2). An upcoming spec update makes this more specific, by requiring a 3.2ms minimum timeout period for the LTTPR detection reading the 0xF0000-0xF0007 range (3.6.5.1). Accordingly disable LTTPR detection until GLK, where the maximum timeout we can set is only 1.6ms. Link training in the non-transparent mode is known to fail at least on some SKL systems with a WD19 dock on the link, which exposes an LTTPR (see the References below). While this could have different reasons besides the too short AUX timeout used, not detecting LTTPRs (and so not using the non-transparent LT mode) fixes link training on these systems. While at it add a code comment about the platform specific maximum timeout values. v2: Add a comment about the g4x maximum timeout as well. (Ville) Reported-by:
Takashi Iwai <tiwai@suse.de> Reported-and-tested-by:
Santiago Zarate <santiago.zarate@suse.com> Reported-and-tested-by:
Bodo Graumann <mail@bodograumann.de> References: https://gitlab.freedesktop.org/drm/intel/-/issues/3166 Fixes: b30edfd8 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: <stable@vger.kernel.org> # v5.11 Cc: Takashi Iwai <tiwai@suse.de> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Bhaskar Chowdhury authored
s/nothign/nothing/ Signed-off-by:
Bhaskar Chowdhury <unixbhaskar@gmail.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210319043701.14105-1-unixbhaskar@gmail.com
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- 18 Mar, 2021 15 commits
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Ankit Nautiyal authored
Remove code for resetting frl related members from intel_disable_dp, as this is not applicable for older platforms. Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
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Jani Nikula authored
Add intel_bios_encoder_data pointer to encoder, and use it for hdmi and dp iboost. For starters, we only set the encoder->devdata for DDI encoders, i.e. we can only use it for data that is used by DDI encoders. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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Jani Nikula authored
Stop caching the information in ddi_port_info. We're phasing out ddi_port_info usage completely, and prefer using the VBT child device information directly using the provided helpers. v2: - Remove supports_typec_usb & supports_tbt from ddi_vbt_port_info (Lucas) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Start using struct intel_bios_encoder_data directly. We'll start sanitizing the child device data directly as well, instead of the cached data in ddi_port_info[]. The one downside here is having to store a non-const pointer back to intel_bios_encoder_data. Eventually we'll be able to have a direct pointer from encoder to intel_bios_encoder_data, removing the need to go through the ddi_port_info[] array altogether. And we'll be able to remove all the cached data in ddi_port_info[]. v2: - Remove supports_dp and supports_edp from ddi_port_info too - Add devdata != NULL check in intel_bios_is_port_edp() Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> # v1 Signed-off-by:
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Jani Nikula authored
We'll be needing the intel_bios_encoder_data pointer going forward, and it's just easier to store the higher level pointer in the ddi_vbt_port_info[] array. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
These will be exposed to the rest of the driver and replace other functions. Everything will operate on the child devices. v2: - Rebased, removed stray blank line - Also abstracted intel_bios_encoder_supports_crt (Lucas) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
We'll be needing it in the future. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Make the naming suitable for exposing to the rest of the driver as an opaque type. No functional changes. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Instead of initialing data directly in ddi_port_info array, create fake child devices for default outputs when the VBT is missing. This makes further unification of output handling easier. This will make intel_bios_is_port_present() return true for the fake child devices. This may cause subtle changes in a handful of places. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
There are two main cases where the default outputs are useful when the VBT is missing: - There are some DDI-platform Chromebooks out there that do not have a VBT, which worked by coincidence because of the default outputs. The machines need to continue to work. - Early platform enabling when the VBT might not be available. (This could be circumvented by using the i915.vbt_firmware parameter.) Prepare for generating fake child devices for the default outputs by limiting the number of outputs. We don't want to generate excessive amounts of fake child devices. This could be perhaps be limited even more in the future, but match what's possible on all DDI platforms. Note that limiting the defaults to non-TypeC ports in commit 828ccb31 ("drm/i915/icl: Add TypeC ports only if VBT is present") is a more strict limit, and makes this a no-op on recent platforms. v2: Rewrote commit message Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Pre-DDI and non-CHV aren't using the information created here anyway, so don't bother setting the defaults for them. This should be a non-functional change, but is separated here to catch any regressions in a single commit. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Unify the code paths at the higher level. Reviewed-by:
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Jani Nikula authored
Reduce indent with an early return. No functional changes. Reviewed-by:
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Jani Nikula authored
We'll be needing the version in more places in the future, so avoid the need to pass it around. No functional changes. v2: Rebased Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1 Signed-off-by:
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Jani Nikula authored
Time to just yank out the bandage. No functional changes. v2: Rebased Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1 Signed-off-by:
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- 17 Mar, 2021 1 commit
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Jani Nikula authored
It's the adls_revid_step_tbl array indexes that matter. Reviewed-by:
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- 16 Mar, 2021 1 commit
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https://github.com/intel/gvt-linuxJani Nikula authored
gvt-next-2021-03-16 - Parse accurate vGPU virtual display rate (Colin) - Convert vblank timer as per-vGPU based on current rate (Colin) - spelling fix (Bhaskar) Signed-off-by:
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- 15 Mar, 2021 3 commits
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Sean Paul authored
One instance of DRM_DEBUG_KMS was leftover in dp_link_training, convert it to the new shiny. Signed-off-by:
Sean Paul <seanpaul@chromium.org> Reviewed-by:
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Sean Paul authored
This patch adds some newlines which are missing from debug messages. This will prevent logs from being stacked up in dmesg. Signed-off-by:
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Umesh Nerlige Ramappa authored
SAMPLE_OA parameter enables sampling of OA buffer and results in a call to init the OA buffer which initializes the OA unit head/tail pointers. The OA_EXPONENT parameter controls the periodicity of the OA reports in the OA buffer and results in starting a hrtimer. Before gen12, all use cases required the use of the OA buffer and i915 enforced this setting when vetting out the parameters passed. In these platforms the hrtimer was enabled if OA_EXPONENT was passed. This worked fine since it was implied that SAMPLE_OA is always passed. With gen12, this changed. Users can use perf without enabling the OA buffer as in OAR use cases. While an OAR use case should ideally not start the hrtimer, we see that passing an OA_EXPONENT parameter will start the hrtimer even though SAMPLE_OA is not specified. This results in an uninitialized OA buffer, so the head/tail pointers used to track the buffer are zero. This itself does not fail, but if we ran a use-case that SAMPLED the OA buffer previously, then the OA_TAIL register is still pointing to an old value. When the timer callback runs, it ends up calculating a wrong/large number of available reports. Since we do a spinlock_irq_save and start processing a large number of reports, NMI watchdog fires and causes a crash. Start the timer only if SAMPLE_OA is specified. v2: - Drop SAMPLE OA check when appending samples (Ashutosh) - Prevent read if OA buffer is not being sampled Fixes: 00a7f0d7 ("drm/i915/tgl: Add perf support on TGL") Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210305210947.58751-1-umesh.nerlige.ramappa@intel.com
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- 12 Mar, 2021 6 commits
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Ville Syrjälä authored
Rename a bunch of the skl+ watermark struct members to have sensible names. Avoids me having to think what plane_res_b/etc. means. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
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Ville Syrjälä authored
Make the code more typo proof by extracting small helpers that do the "do we have enough DDB for the WM level?" checks in a consistent manner. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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Ville Syrjälä authored
Let's make all the "do we have enough DDB for this WM level?" checks use min_ddb_alloc. To achieve that we need to populate this for the transition watermarks as well. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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Ville Syrjälä authored
For non-transition watermarks we are supposed to check min_ddb_alloc rather than plane_res_b when determining if we have enough DDB space for it. A bit too much copy pasta made me check the wrong thing. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: df4a50a3 ("drm/i915: Zero out SAGV wm when we don't have enough DDB for it") Signed-off-by:
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Ville Syrjälä authored
Say we have two planes enabled with watermarks configured as follows: plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true plane B: wm0=enabled/can_sagv=true, wm1=disabled This is possible since the latency we use to calculate can_sagv may not be the same for both planes due to skl_needs_memory_bw_wa(). In this case skl_crtc_can_enable_sagv() will see that both planes have enabled at least one watermark level with can_sagv==true, and thus proceeds to allow SAGV. However, since plane B does not have wm1 enabled plane A can't actually use it either. Thus we are now running with SAGV enabled, but plane A can't actually tolerate the extra latency it imposes. To remedy this only allow SAGV on if the highest common enabled watermark level for all active planes can tolerate the extra SAGV latency. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
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Ville Syrjälä authored
On HSW/BDW with VT-d active the first tile row scanned out after the first async flip of the frame often ends up corrupted. Whether the corruption happens or not depends on the scanline on which the async flip happens, but the behaviour seems very consistent. Ie. the same set of scanlines (which are most scanlines) always show the corruption. And another set of scanlines (far less of them) never shows the corruption. I discovered that disabling the fetch-stride stretching feature cures the corruption. This is some kind of TLB related prefetch thing AFAIK. We already disable it on SNB primary planes due to a documented workaround. The hardware folks indicated that disabling this should be fine, so let's go with that. And while we're here, let's document the relevant bits on all pre-skl platforms. Fixes: 2a636e24 ("drm/i915: Implement async flip for ivb/hsw") Fixes: cda195f1 ("drm/i915: Implement async flips for bdw") Signed-off-by:
Karthik B S <karthik.b.s@intel.com>
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- 11 Mar, 2021 2 commits
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Ville Syrjälä authored
Let's check that we actually found the PLL before doing the port_clock readout, just in case the hardware was severly misprogrammed by the previous guy. Not sure the hw would even survive such misprogramming without hanging but no real harm in checking anyway. Cc: Karthik B S <karthik.b.s@intel.com> Signed-off-by:
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Jani Nikula authored
Sync up with upstream. Signed-off-by:
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- 08 Mar, 2021 1 commit
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Ville Syrjälä authored
Now that all the encoder clock stuff is uniformly abstracted for all hsw+ platforms, let's extend icl_sanitize_encoder_pll_mapping() to cover all of them. Not sure there is a particular benefit in doing so, but less special cases always makes me happy. Signed-off-by:
Mika Kahola <mika.kahola@intel.com>
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