- 09 Nov, 2023 14 commits
-
-
Yang Wang authored
refine smu mca driver to support query ras error from pmfw path. - correct gfx smu bank hwid (from mp5 to smu bank) - retire unused callback function in amdgpu_mca_smu_funcs{} - add new mca_bank_set{} structure to collect mca bank - move enum mca_reg_idx into amdgpu_mca.h header - add mca status register field decode macro Signed-off-by:Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Victor Lu authored
The following regs can only be programmed by the PF: HDP_MISC_CNTL HDP_NONSURFACE_BASE HDP_NONSURFACE_BASE_HI v2: update commit message Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
Samir Dhume <samir.dhume@amd.com> Signed-off-by:
-
Victor Lu authored
PCTL0_MMHUB_DEEPSLEEP_IB is blocked for VF access Signed-off-by:
-
Hunter Chasens authored
Resolves Sphinx unexpected indentation warning when compiling documentation (e.g. `make htmldocs`). Replaces tabs with spaces and adds a literal block to keep vertical formatting of the example power state list. Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Bagas Sanjaya <bagasdotme@gmail.com> (v2) Acked-by: Randy Dunlap <rdunlap@infradead.org> (v2) Signed-off-by:
Hunter Chasens <hunter.chasens18@ncf.edu> Signed-off-by:
-
Yang Wang authored
correct smu v13.0.0 umc ras error check Signed-off-by:
-
Victor Lu authored
WREG32/RREG32_SOC15_IP_NO_KIQ and amdgpu_virt_kiq_reg_write_reg_wait are not using the correct rlcg interface or mec engine, respectively. Add xcc instance parameter to them. v4: Use GET_INST and squash commit with: "drm/amdgpu: Add xcc_inst param to amdgpu_virt_kiq_reg_write_reg_wait" v3: xcc not needed for MMMHUB v2: rebase Signed-off-by:
-
Victor Lu authored
The "rlcg_reg_access_supported" flag is missing. Add it back in. Signed-off-by:
-
Le Ma authored
The DS clock may exceed the limit as sclk dfll divider is 16 to target freq. Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
-
Yang Wang authored
correct following amdgpu ip block version information: - gfx_v9_4_3 - sdma_v4_4_2 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
-
Lijo Lazar authored
Hide PCIe DPM attribute on SOCs with GC v9.4.2 and GC v9.4.3. Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
-
Tao Zhou authored
set_xgmi_plpd_mode may be unsupported and this isn't error, no need to print warning for it. v2: add ret2 to save the status of psp_ras_trigger_error. Suggested-by: lijo.lazar@amd.com Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
-
Christian König authored
Otherwise userspace can spam the logs by using incorrect input values. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
-
Christian König authored
We should not leak the pointer where we couldn't grab the reference on to the caller because it can be that the error handling still tries to put the reference then. Signed-off-by:
-
Alex Deucher authored
The default AGP settings were overwriting the IP selected ones since the default was getting set after the IP ones were selected. Fixes: de59b699 ("drm/amdgpu/gmc: set a default disable value for AGP") Link: https://lists.freedesktop.org/archives/amd-gfx/2023-November/100966.htmlTested-by:
Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Reviewed-by:
-
- 07 Nov, 2023 26 commits
-
-
Tao Zhou authored
Reset/query RAS error status and count. v2: use XGMI IP version instead of WAFL version. Signed-off-by:
-
Tao Zhou authored
The UE registe list is larger than CE list. Reported-by: yipeng.chai@amd.com Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by:
-
Tim Huang authored
For IMU enabled APUs, after sending the PrepareMp1ForUnload message to SMU in system_features_control, the RLC registers can't be touched. The driver to stop the rlc in suspending is no longer required. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
-
Bragatheswaran Manickavel authored
The member variable enable_hpo_pg_support is already initialized and hence the reinitialization instruction can be removed. Issue identified using the doubleinit.cocci Coccinelle semantic patch script. Signed-off-by:
Bragatheswaran Manickavel <bragathemanick0908@gmail.com> Signed-off-by:
-
Lijo Lazar authored
Change return code to EOPNOTSUPP for unsupported functions. Use the error code information to hide sysfs nodes not valid for the SOC. Signed-off-by:
-
Lijo Lazar authored
Doorbell rptr/wptr can be set through multiple ways including direct register initialization. Disable doorbell during hw_fini once the ring is disabled so that during next module reload direct initialization takes effect. Also, move the direct initialization after minor update is set to 1 since rptr/wptr are reinitialized back to 0 which could be lower than the previous doorbell value (ex: cases like module reload). Signed-off-by:
-
Jiadong Zhu authored
Set the default reset method to mode2 for SMU IP v14.0.0 Signed-off-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by:
-
George Shen authored
[Why] A recent refactor of DC's DP test pattern automation code requires the DC stream's test pattern and test pattern color space fields to be correctly populated before calling dc_link_dp_set_test_pattern. [How] Populate stream's test pattern type and color space fields before calling into DC to program DP test pattern. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Hersen Wu <hersenxs.wu@amd.com> Signed-off-by:
George Shen <george.shen@amd.com> Signed-off-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
-
Sung Joon Kim authored
[why] DML2 does not handle the case when we have a single stream sourcing 2 or more planes that are duplicates of one another. To properly handle this scenario, pipe index to plane index mapping is used to decide which plane is being processed and programmed. [how] Create static array of pipe index to plane index map. Populate the array properly and use in appropriate places. Reviewed-by:
Xi (Alex) Liu <xi.liu@amd.com> Acked-by:
Sung Joon Kim <sungkim@amd.com> Signed-off-by:
-
Alvin Lee authored
[Description] - Similar to FPO, SubVP should also force cursor P-State allow instead of relying on natural assertion - Implement code path to force and unforce cursor P-State allow for SubVP Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
-
Daniel Miess authored
[Why] Enable the last of the RCO options for dcn35 [How] Breakout RCO from dccg35_set_physymclk so that physymclk RCO can be set in dccg_init without disabling physymclk Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Daniel Miess <daniel.miess@amd.com> Signed-off-by:
-
Chaitanya Dhere authored
Clean-up the code to remove references of all unused dml architecture versions since only dml2 is actively used. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Signed-off-by:
-
Aric Cyr authored
Summary: - Enable DCN35 physymclk root clock gating - Fix DP automation test pattern bug - Disable OTG for mode timing switch on DCN35 - Refactor DML2 - Revert Fix handling duplicate planes on one stream - Revert Enable DCN clock gating - Implement cursor P-State allow for SubVP - Optimize pipe otg allocation - Save and restore mall state while switching from ODM to Subvp Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
-
Wenjing Liu authored
[why] There is a case when we are switching from ODM combine to Subvp where minimal transition based off subvp state is required. In thise case, we need to save and restore mall state when applying minimal transition. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
-
Joshua Aberback authored
[Why] DCN32 uses ABM register definitions in dcn32_resource.h, remove duplicate from dce_abm.h to avoid confusion. Reviewed-by:
Joshua Aberback <joshua.aberback@amd.com> Signed-off-by:
-
Rodrigo Siqueira authored
For all the components that participate in DCN architecture, there is a header in the dc/inch/hw. For some reason, OPTC broke this pattern and added all the primary functions/structs associated with that in the dcn10_optc.h file. For consistency's sake, this commit introduces a new optc.h file and extracts the code from dcn10_optc to this new file. Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by:
-
Ovidiu Bunea authored
[why] Doing a mode timing change causes a hang when OTG is not disabled. [how] Add link_enc null check in disable_otg_wa to cover this case. Reviewed-by:
Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by:
-
Dennis Chan authored
[Why] Current Desync IRQ handler will have some potential do not hit the desync error case. We change to check both desync error HPD and DPCD. Signed-off-by:
Dennis Chan <dennis.chan@amd.com> Acked-by:
Robin Chen <robin.chen@amd.com> Tested-by:
-
Anthony Koo authored
- Increase number of bits for IPS boot option Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
-
Aric Cyr authored
This version brings along following fixes: Update test link rate DPCD bit field to match spec Enable RCO options for dcn35 Add missing dml2 init value for dcn35 Enable DCN clock gating DCN35 Disable cm power optimization Allow 16 max_slices for DP2 DSC Fix OTG disable workaround logic Enable more IPS options Fix FRL assertion on boot Fix missing blendTF programming Update DP HPO MSA with colorimetry from test request Fix handling duplicate planes on one stream Acked-by:
-
Roman Li authored
[Why] For lighting up, some dml2 params needs to be initialized. One of them escaped initial patch under: "drm/amd/display: Add DCN35 DML2 support" [How] Add missing initialization. Fixes: 115009d1 ("drm/amd/display: Add DCN35 DML2 support") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
-
Taimur Hassan authored
[Why] DENTIST was hanging when performing DISPCLK update with OTG enabled, as OTG disable workaround was not executing. [How] Workaround was checking against current_state before running, but when called from optimize_bandwidth (safe_to_lower), we should be checking against context instead. Reviewed-by:
Taimur Hassan <syed.hassan@amd.com> Tested-by:
-
ChunTao Tso authored
[Why] For Replay, if we receive HPD, it doesn’t need to reboot the display. We don’t need to return anything exactly. [How] Return nothing just because we don’t need to reboot the display. Signed-off-by:
ChunTao Tso <chuntao.tso@amd.com> Acked-by:
Jerry Zuo <jerry.zuo@amd.com> Tested-by:
-
Dennis Chan authored
[why] It's useful to disable the recovery mechanism when debugging replay desync errors. Signed-off-by:
-
Yihan Zhu authored
[WHY & HOW] Enabling SCE after boot up will cause color distortion. Reviewed-by:
Yihan Zhu <yihan.zhu@amd.com> Tested-by:
-
George Shen authored
[Why] Some DP link layer tests request a different colorimetry than the default one that is used. Currently, our test automation logic does not update the MSA with the test request value for DP HPO case. [How] Update HPO MSA colorimetry with test automation request value. Reviewed-by:
-
