- 23 Dec, 2022 1 commit
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Jouni Högander authored
Currently we are observing occasionally display flickering or complete freeze. This is narrowed down to be caused by single full frame update (SFF). SFF bit after it's written gets cleared by HW in subsequent vblank i.e. when the update is sent to the panel. SFF bit is required to be written together with partial frame update (PFU) bit. After the SFF bit gets cleared by the HW psr2 man trk ctl register still contains PFU bit. If there is subsequent update for any reason we will end up having selective update/fetch configuration where start line is 0 and end line is 0. Also selective fetch configuration for the planes is not properly performed. This seems to be causing problems with some panels. Using CFF without SFF doesn't work either because it may happen that psr2 man track ctl register is overwritten by next update before vblank triggers sending the update. This is causing problems to psr_invalidate/flush. Using CFF and SFF together solves the problems as SFF is cleared only by HW in subsequent vblank and the update gets sent. Fix the flickering/freeze issue by keeping CFF bit as set when PSR2 is enabled unless there is a properly configured selective update via atomic commit. v2: - Improve commit message and comments - No functional changes This is also workaround for HSD 14014971508 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Reported-by:
Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Tested-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221201072308.1905679-1-jouni.hogander@intel.com
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- 22 Dec, 2022 1 commit
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Jani Nikula authored
Due to copy-paste fail, MIPI_BKLT_EN_1 would always use PPS index 1, never 0. Fix the sloppiest commit in recent memory. Fixes: f087cfe6 ("drm/i915/dsi: add support for ICL+ native MIPI GPIO sequence") Reported-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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- 21 Dec, 2022 2 commits
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Ankit Nautiyal authored
After enabling DDI_BUF_CTL, wait for DDI_BUF_CTL to be active. Bspec:4232,53339,49191,54145 Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Ankit Nautiyal authored
For Gen12+ wait for 1ms for Combo Phy and 3ms for TC Phy for DDI_BUF_CTL to be active for TC phy. (Bspec:49190) v2: Minor refactoring for better readability. v3: Rebased and retained the order of checking platforms. (Imre) Signed-off-by:
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- 20 Dec, 2022 1 commit
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Jani Nikula authored
Starting from ICL, the default for MIPI GPIO sequences seems to be using native GPIOs i.e. GPIOs available in the GPU. These native GPIOs reuse many pins that quite frankly seem scary to poke based on the VBT sequences. We pretty much have to trust that the board is configured such that the relevant HPD, PP_CONTROL and GPIO bits aren't used for anything else. MIPI sequence v4 also adds a flag to fall back to non-native sequences. v5: - Wrap SHOTPLUG_CTL_DDI modification in spin_lock() in icp_irq_handler() too (Ville) - References instead of Closes issue 6131 because this does not fix everything v4: - Wrap SHOTPLUG_CTL_DDI modification in spin_lock_irq() (Ville) v3: - Fix -Wbitwise-conditional-parentheses (kernel test robot <lkp@intel.com>) v2: - Fix HPD pin output set (impacts GPIOs 0 and 5) - Fix GPIO data output direction set (impacts GPIOs 4 and 9) - Reduce register accesses to single intel_de_rwm() References: https://gitlab.freedesktop.org/drm/intel/-/issues/6131 Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 16 Dec, 2022 2 commits
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Lucas De Marchi authored
The attribute __maybe_unused should remain only until the respective info is not in the pciidlist. The info can't be added together with its definition because that would cause the driver to automatically probe for the device, while it's still not ready for that. However once pciidlist contains it, the attribute can be removed. Fixes: 78353039 ("drm/i915/mtl: Add MeteorLake PCI IDs") Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221214194944.3670344-1-lucas.demarchi@intel.com
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Lucas De Marchi authored
While debugging page table faults it's useful not to kill the machine with thousands of error mesages. Ratelimit all errors in gen8_de_irq_handler(). Signed-off-by:
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- 13 Dec, 2022 19 commits
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Stanislav Lisovskiy authored
Fix intel_dp_dsc_compute_config, previously timeslots parameter was used in fact not as a timeslots, but more like a ratio timeslots/64, which of course didn't have any effect for SST DSC, but causes now issues for MST DSC. Secondly we need to calculate pipe_bpp using intel_dp_dsc_compute_bpp only for SST DSC case, while for MST case it has been calculated earlier already with intel_dp_dsc_mst_compute_link_config. Third we also were wrongly determining sink min bpp/max bpp, those limites should be intersected with our limits to find common acceptable bpp's, plus on top of that we should align those with VESA bpps and only then calculate required timeslots amount. Some MST hubs started to work only after third change was made. v2: Make kernel test robot happy(claimed there was unitialzed use, while there is none) v3: Rename intel_dp_dsc_nearest_vesa_bpp to intel_dp_dsc_nearest_valid_bpp (Manasi Navare) Reviewed-by:Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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Stanislav Lisovskiy authored
We might to use that function separately from intel_dp_dsc_compute_config for DP DSC over MST case, because allocating bandwidth in that case can be a bit more tricky. So in order to avoid code copy-pasta lets extract this to separate function and reuse it for both SST and MST cases. v2: Removed multiple blank lines v3: Rename intel_dp_dsc_nearest_vesa_bpp to intel_dp_dsc_nearest_valid_bpp to reflect its meaning more properly. (Manasi Navare) Signed-off-by: -
Stanislav Lisovskiy authored
Whenever we are not able to get enough timeslots for required PBN, let's try to allocate those using DSC, just same way as we do for SST. v2: Removed intel_dp_mst_dsc_compute_config and refactored intel_dp_dsc_compute_config to support timeslots as a parameter(Ville Syrjälä) v3: - Rebased - Added a debug to see that we at least try reserving VCPI slots using DSC, because currently its not visible from the logs, thus making debugging more tricky. - Moved timeslots to numerator, where it should be. v4: - Call drm_dp_mst_atomic_check already during link config computation, because we need to know already by this moment if uncompressed amount of VCPI slots needed can fit, otherwise we need to use DSC. (thanks to Vinod Govindapillai for pointing this out) v5: - Put pipe_config->bigjoiner_pipes back to original condition in intel_dp_dsc_compute_config (don't remember when I lost it) v6: - Removed unnecessary drm_dp_mst_atomic_check as it is now always called in a newly introduced intel_dp_mst_find_vcpi_slots_for_bpp function (Vinod Govindapillai) Reviewed-by:Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by:
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Stanislav Lisovskiy authored
We would be using almost same code to loop through bpps while calling drm_dp_atomic_find_vcpi_slots - lets remove this duplication by introducing a new function intel_dp_mst_find_vcpi_slots_for_bpp v2: Fix pbn_div calculation - shouldn't matter if its DSC or not. v3: FIx rebase conflict, constant_n no longer needed. Reviewed-by:
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Stanislav Lisovskiy authored
We currently always exit that bpp loop because drm_dp_atomic_find_vcpi_slots doesn't care if we actually can fit those or not. I think that wasn't the initial intention here, especially when we keep trying with lower bpps, we are supposed to keep trying until we actually find some _working_ configuration, which isn't the case here. So added that drm_dp_mst_check here, so that we can make sure that try all the bpps before we fail. Reviewed-by:
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Stanislav Lisovskiy authored
Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
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Jani Nikula authored
Add a new sub-directory for things that aren't specifically about the GPU and don't really belong in the i915 driver top level, but also don't belong under any of the existing sub-directories either. Name it "soc", and move the PCH and DRAM code there. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ville Syrjälä authored
We could use the dsb to load the LUT in any gamma mode, not just when using the multi-segment mode. So replace the direct mmio on all ilk+ paths with the wrapper. There are a few functions (ilk_load_lut_10(), ivb_load_lut_10()) that would never be used on a platform with dsb so we could skip those, but probably better to keep all this 100% consistent to avoid people getting confused and copy pasting the wrong thing when adding a new gamma mode. The gmch stuff I left with direct mmio since those are fairly distinct and shouldn't cause too much confusion. Although I've also pondered about converting everything over to dsb command buffers and just executing it on the CPU when the real hw is not available. But dunno if that would actually be a good idea or not... Signed-off-by:
Uma Shankar <uma.shankar@intel.com>
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Ville Syrjälä authored
This reverts commit 99510e1a. DSB is now getting disabled locally in the color management code so we don't need to apply this big hammer via the device info (not that we have other DSB users at the moment). Signed-off-by:
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Ville Syrjälä authored
The DSB has problem loading the LUTs at the moment. Some of that is due to the palette anti collision logic, some due to what seem real hw issues. Disable it the whole thing locally in the color management code for now. Note that we currently have this weird situation where on adl+ we load parts of the LUT with DSB and parts with mmio. That is due to the fact that only some parts of the LUT code are using the DSB register write functions (ivb_load_lut_ext*()), while the rest is using pure mmio (bdw_load_lut_10()). So now we'll go back to pure mmio temporarily, until the DSB issues get fixed (at which point we should be going for pure DSB). Signed-off-by:
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Ville Syrjälä authored
We could have many different uses for the DSB(s) during a single commit, so the current approach of passing the whole crtc_state to the DSB functions is far too high level. Lower the abstraction a little bit so each DSB user can decide where to stick the command buffer/etc. v2: Document the intel_dsb_prepare() return value (Ankit) Signed-off-by:
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Ville Syrjälä authored
Since the color management code is the only user of the DSB at the moment move the DSB prepare/cleanup there too. The code has to anyway make decisions on whether to use the DSB or not (and how to use it). Also we'll need a place where we actually generate the DSB command buffer ahead of time rather than the current situation where it gets generated too late during the mmio programming of the hardware. Signed-off-by:
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Ville Syrjälä authored
The use of DSB has to be done differently on a case by case basis. So no way this kind of blind mmio fallback in the guts of the DSB code will work properly. Move it at least one level up into the LUT loading code. Not sure if this is the way we want do the DSB vs. mmio handling in the end, but at least it's a bit closer than what we had before. Signed-off-by:
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Ville Syrjälä authored
Document the precision of the LUT "max" registers, just so we don't have to dig through the spec so much. Signed-off-by:
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Ville Syrjälä authored
Various gamma units on various platforms have some problems loading the LUT index and auto-increment bit at the same time. We have to do this in two steps. The first known case was the glk degamma LUT, but at least ADL has another known case. We're not going to suffer too badly from a couple of extra register writes here, so let's just standardize on this practice for all auto-increment LUT loads/reads. This way we never have to worry about this specific issue again. And for good measure always reset the index back to zero at the end (we already did this in a few places). Signed-off-by:
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Ville Syrjälä authored
Use REG_BIT() & co. for the LUT index registers, and also use the REG_FIELD_PREP() stuff a bit more consistently when generating the values for said registers. Signed-off-by:
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Ville Syrjälä authored
I've been frobbing the palette anti-collision logic bit while playing around with DSB. Not sure we'll have real use for this but let's define the bit anyways so I don't have to carry it around locally. Signed-off-by:
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Ville Syrjälä authored
Use REG_BIT() & co. for GAMMA_MODE bits. Signed-off-by:
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Ville Syrjälä authored
s/GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED/GAMMA_MODE_MODE_12BIT_MULTI_SEG/ to make this thing slightly shorter. Also fix up the platform comment while at it. Signed-off-by:
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- 12 Dec, 2022 1 commit
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Jouni Högander authored
This patch introduces initial workarounds for mtl platform v2: switch IS_MTL_DISPLAY_STEP to use IS_METEORLAKE from testing display ver. (Tvrtko) v3: clerical issues, extend 16015201720 to mtl. (MattR) v4: make sure 16015201720 includes display 13. (MattR) Bspec: 66624 Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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- 09 Dec, 2022 11 commits
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Ville Syrjälä authored
Always include both the encoder and PPS instance information in the debug prints so that we know what piece of hardware we're actually dealing with. v2: Make sure pps is selected before debug prints/etc. in intel_pps_vdd_on_unlocked() on vlv/chv There is no pps on pipe C on chv v3: Allow PPS=INVALID_PIPE for vlv/chv Cc: Animesh Manna <animesh.manna@intel.com> Signed-off-by:Animesh Manna <animesh.manna@intel.com>
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Ville Syrjälä authored
Stray spaces have snuck in where everything else uses tabs. Cc: Animesh Manna <animesh.manna@intel.com> Signed-off-by:
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Ville Syrjälä authored
Use the consistent format when dumping out the PPS control/status registers. Helps with pattern matching. Cc: Animesh Manna <animesh.manna@intel.com> Signed-off-by:
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Ville Syrjälä authored
On ICP-ADP the pins used by the second PPS can be alternatively muxed to some other function. In that case the second power sequencer is unusable. Unfortunately (on my ADL Thinkpad T14 gen3 at least) the BIOS still likes to enable the VDD on the second PPS (due to the VBT declaring the second bogus eDP panel) even when not correctly muxed, so we need to deal with it somehow. For now let's just initialize the PPS as normal, and then use the normal eDP probe failure VDD off path to turn it off (and release the wakeref the PPS init grabbed). The alternative of just declaring that the platform has a single PPS doesn't really work since it would cause the second eDP probe to also try to use the first PPS and thus clobber the state for the first (real) eDP panel. Cc: Animesh Manna <animesh.manna@intel.com> Signed-off-by:
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Ville Syrjälä authored
On the PCH side the second PPS was introduced in ICP. Let's make sure we examine both power sequencer on ICP+ as well. Note that DG1/2 south block only has the single PPS, so need to exclude the fake DG1/2 PCHs. Cc: Animesh Manna <animesh.manna@intel.com> Signed-off-by:
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Ville Syrjälä authored
Currently on bxt/glk we just grab the power sequencer index from the VBT data even though it may not have been parsed yet. That could lead us to using the incorrect power sequencer during the initial panel probe. To avoid that let's try to read out the current state of the power sequencer from the hardware. Unfortunately the power sequencer no longer has anything in its registers to associate it with the port, so the best we can do is just iterate through the power sequencers and pick the first one. This should be sufficient for single panel cases. For the dual panel cases we probably need to go back to parsing the VBT before the panel probe (and hope that panel_type=0xff is never a thing in those cases). To that end the code always prefers the VBT panel sequencer, if available. v2: Restructure a bit for upcoming icp+ dual PPS support Cc: Animesh Manna <animesh.manna@intel.com> Signed-off-by:
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Ville Syrjälä authored
Restate the vlv_pipe_check() stuff in terms of PPS index (rather than pipe, which it is on VLV/CHV) so that we can reuse this same mechanim on other platforms as well. Cc: Animesh Manna <animesh.manna@intel.com> Reviewed-by:
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Ville Syrjälä authored
Lots of ADL machines out there with bogus VBTs that declare two eDP child devices. In order for those to work we need to figure out which power sequencer to use before we try the EDID read. So let's do the panel VBT init early if we can, falling back to the post-EDID init otherwise. The post-EDID init panel_type=0xff approach of assuming the power sequencer should already be enabled doesn't really work with multiple eDP panels, and currently we just end up using the same power sequencer for both eDP ports, which at least confuses the wakeref tracking, and potentially also causes us to toggle the VDD for the panel when we should not. Cc: Animesh Manna <animesh.manna@intel.com> Reviewed-by:
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Ville Syrjälä authored
Introduce a place where we can initialize connector->panel after it's been allocated. We already have a intel_panel_init() so had to get creative with the name and came up with intel_panel_init_alloc(). Cc: Animesh Manna <animesh.manna@intel.com> Reviewed-by:
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Jani Nikula authored
Remove an unnecessary include. Signed-off-by:
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Khaled Almahallawy authored
Bspecs has updated recently to remove the restriction to disable DDI/Transcoder before setting PHY test pattern. This update is to address PHY compliance test failures observed on a port with LTTPR. The issue is that when Transc. is disabled, the main link signals fed to LTTPR will be dropped invalidating link training, which will affect the quality of the phy test pattern when the transcoder is enabled again. v2: Update commit message (Clint) v3: Add missing Signed-off in v2 v4: Update Bspec and commit message for pre-gen12 (Jani) Bspec: 50482, 7555 Fixes: 8cdf7271 ("drm/i915/dp: Program vswing, pre-emphasis, test-pattern") Cc: Imre Deak <imre.deak@intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> CC: Jani Nikula <jani.nikula@intel.com> Tested-by:
Khaled Almahallawy <khaled.almahallawy@intel.com> Reviewed-by:
Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
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- 08 Dec, 2022 2 commits
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Ville Syrjälä authored
On mtl (at least) clearing the guardband bits in the same write as the enable bit gets cleared seems to cause an immediate FIFO underrun. Thus is seems that we need to first clear just the enable bit, then wait for the VRR live status to indicate the transcoder has exited VRR mode (this step is documented in Bspec as well), and finally we can clear out the rest of the TRANS_VRR_CTL for good measure. I did this without any RMWs in case we want to toggle VRR on/off via DSB in the future, and as we know DSB can't read registers. Signed-off-by:
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Ville Syrjälä authored
On mtl it looks like disabling VRR after the transcoder has been disabled can cause the pipe/transcoder to get stuck when re-enabled in non-vrr mode. Reversing the order seems to help. Bspec is extremely confused about the VRR enable/disable sequence anyway, and this now more closely matches the non-modeset VRR sequence, whereas the full modeset sequence still claims that the original order is fine. But since we eventually want to toggle VRR without a full modeset anyway this seems like the better order to follow. Signed-off-by:
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