- 27 Aug, 2019 10 commits
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Evan Quan authored
Correct the settings for auto mode and skip the unnecessary settings for dcefclk and fclk. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Implement HW I2C enigne controller to be used by the RAS EEPROM table manager. This is based on code from ATITOOLs. v2: Rename the file and all function prefixes to smu_v11_0_i2c By Luben's observation always fill the TX fifo to full so we don't have garbadge interpreted by the slave as valid data. v3: Remove preemption disable as the HW I2C controller will not stop the clock on empty TX fifo and so it's not critical to keep not empty queue. Switch to fast mode 400 khz SCL clock for faster read and write. v5: Restore clock gating before releasing I2C bus and fix some style comments. v6: squash in warning fix, fix includes (Alex) Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Luben Tuikov <Luben.Tuikov@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
v2: PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict over I2C bus and engine disable thermal control access to force SMU stop using the I2C bus until the issue is reslolved. Expose and call vega20_is_smc_ram_running to skip locking when SMU FW is not yet loaded. v3: Remove the prevoius hack as the SMU found the bug. v5: Typo fix Signed-off-by:
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Andrey Grodzovsky authored
v3: Merge CKSVII2C_IC regs into exsisting headers. Signed-off-by:
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Andrey Grodzovsky authored
Add RAS EEPROM table manager to eanble RAS errors to be stored upon appearance and retrived on driver load. v2: Fix some prints. v3: Fix checksum calculation. Make table record and header structs packed to do correct byte value sum. Fix record crossing EEPROM page boundry. v4: Fix byte sum val calculation for record - look at sizeof(record). Fix some style comments. v5: Add description to EEPROM_TABLE_RECORD_SIZE and syntax fixes. Signed-off-by:
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Gang Ba authored
This reverts commit 4f8bc72f. It turned out that a single reserved queue wouldn't be sufficient for page fault handling. Signed-off-by:
Gang Ba <gaba@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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YueHaibing authored
If CONFIG_DRM_AMD_DC_DSC_SUPPORT is not set, build fails: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c: In function dcn20_hw_sequencer_construct: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hwseq.c:2099:28: error: dcn20_dsc_pg_control undeclared (first use in this function); did you mean dcn20_dpp_pg_control? dc->hwss.dsc_pg_control = dcn20_dsc_pg_control; ^~~~~~~~~~~~~~~~~~~~ dcn20_dpp_pg_control Use CONFIG_DRM_AMD_DC_DSC_SUPPORT to guard this. Reported-by:Hulk Robot <hulkci@huawei.com> Fixes: 8a31820b ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Dan Carpenter authored
The navi10_message_map[] array has SMU_MSG_MAX_COUNT elements so the ">" has to be changed to ">=" to prevent reading one element beyond the end of the array. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Andrey Grodzovsky authored
Since reservation_object_wait_timeout_rcu is called with interruptable set to false it's wrong to say 'or interrupted' in the error message. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
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Xiaojie Yuan authored
The GRBM register interface is now capable of bursting 1 cycle per register wr->wr, wr->rd much faster than previous muticycle per transaction done interface. This has caused a problem where status registers requiring HW to update have a 1 cycle delay, due to the register update having to go through GRBM. SW may operate on an incorrect value if they write a register and immediately check the corresponding status register. Registers requiring HW to clear or set fields may be delayed by 1 cycle. For example, 1. write VM_INVALIDATE_ENG0_REQ mask = 5a 2. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a a. HW will reset VM_INVALIDATE_ENG0_ACK = 0 until invalidation is complete 3. write VM_INVALIDATE_ENG0_REQ mask = 5a 4. read VM_INVALIDATE_ENG0_ACK till the ack is same as the request mask = 5a a. First read of VM_INVALIDATE_ENG0_ACK = 5a instead of 0 b. Second read of VM_INVALIDATE_ENG0_ACK = 0 because the remote GRBM h/w register takes one extra cycle to be cleared c. In this case, SW will see a false ACK if they exit on first read Affected registers (only GC variant) | Recommended Dummy Read --------------------------------------+---------------------------- VM_INVALIDATE_ENG*_ACK | VM_INVALIDATE_ENG*_REQ VM_L2_STATUS | VM_L2_STATUS VM_L2_PROTECTION_FAULT_STATUS | VM_L2_PROTECTION_FAULT_STATUS VM_L2_PROTECTION_FAULT_ADDR_HI/LO32 | VM_L2_PROTECTION_FAULT_ADDR_HI/LO32 VM_L2_IH_LOG_BUSY | VM_L2_IH_LOG_BUSY MC_VM_L2_PERFCOUNTER_HI/LO | MC_VM_L2_PERFCOUNTER_HI/LO ATC_L2_PERFCOUNTER_HI/LO | ATC_L2_PERFCOUNTER_HI/LO ATC_L2_PERFCOUNTER2_HI/LO | ATC_L2_PERFCOUNTER2_HI/LO Signed-off-by:Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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- 23 Aug, 2019 30 commits
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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hersen wu authored
[WHY] value of dchub_ref_clock is decided by dchubbub global timer settings which is programmed by vbios command table disp_init. for multi-GPU case, vbios is posted only for primary GPU. without vbios posted for the secondary GPU, value of dchub_ref_clock is not set properly. this value will affect dcn bandwidth calcuation and cause underflow. user will see screen flicking during driver installation for dual GPU case. [HOW] dc init_hw always call vbios command table disp_init to make sure dchubbub global timer is configured and enable. Signed-off-by:
hersen wu <hersenxs.wu@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Joshua Aberback authored
[Why] The register LVTMA_PWRSEQ_CNTL is used to determine the power state of the embedded display. Currently we do not actually read this register's values, so during power down we think that this display is already off, so we skip calling into VBIOS to actually turn it off. [How] - add relevant fields to shift / mask initialization Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Jun Lei authored
[why] Previous workaround to prevent a vsync flip to be converted to immediate flip is no longer needed, and is risky because there are cases where it can result in infinite loop. [how] Remove wait loop (which is potentially infinite) before locking pipe Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Derek Lai authored
[Why] We should be using the ddc_num from res_caps. As the pipe count != number of i2c resources. [How] Use ddc_num from res_cap instead of pipe count. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
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Bayan Zabihiyan authored
[Why] Existing HW Features, HW Diags test requested that the registers be exposed. [How] Add V_TOTAL_MID to existing DC structures. Make sure values are passed down throughout DC Add Register definition. Program the additional registers Add additional Logic for V_TOTAL_CONTROL. Signed-off-by:
Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by:
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Jun Lei authored
[why] Calculating DCFCLK DS time requires calculating delivery time for luma/chroma, but this value is not calculated in DMLv2, it was inadvertently removed when porting DMLv2 [how] Add the calculation back Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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David Francis authored
DRM provides drm_dp_mst_dump_topology, which prints useful information about MST devices Hook this up to a debugfs file named amdgpu_mst_topology Signed-off-by:
David Francis <David.Francis@amd.com> Acked-by:
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Charlene Liu authored
[Description] OS will reserve HW state in UEFI mode. Driver init_hw reset to RGB which caused HDMI green in YCbCr mode. read HW blank_color based on acc_mode. Signed-off-by:
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Wyatt Wood authored
[Why] A recent bug showed that logging would be useful in debugging various gamma issues. [How] Add logging in dc. Fix formatting for easier graphing. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
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Jaehyun Chung authored
[Why] HW rotation is not enabled. Calculations for cursor rotation are wrong for the values passed to set_cursor_position. [How] Swap Src rect and height and vertically mirror surface for the correct surface rotation direction. Cursor position is rotated according to angle. Offset calculations are tweaked for non-rotated cursor hotspot and width/height. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
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Bayan Zabihiyan authored
[Why] We need to have the ability to to tell us set degamma on the cursor. [How] Pass a flag down to register programming that tells us if the current surface format needs cursor degamma. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Update bw validation to use prev and next odm pipe pointers for populating dml inputs. Signed-off-by:
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Dmytro Laktyushkin authored
Need to memset all odm pipes when calling dc_remove_stream_from_ctx Signed-off-by:
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Dmytro Laktyushkin authored
dcn20 requires special casing for odm. This change treats odm as alternative to mpc tree on dcn20. This is planned to be fixed in a future refactor Signed-off-by:
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Nikola Cornij authored
[why] num_slices_h was not being checked [How] Fix the typo and check num_slices_h Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
ODM next and prev pipe were missing from dc_copy_state Signed-off-by:
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Yogesh Mohan Marimuthu authored
[Why] In newer hardware MANUAL_FLOW_CONTROL is not a trigger bit. Due to this front porch is fixed and in these hardware freesync does not work. [How] Change the programming to generate a pulse so that the event will be triggered, front porch will be cut short and freesync will work. Signed-off-by:
Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by:
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Zi Yu Liao authored
[why] With visual confirm enabled, displays where ODM combine is enabled has a test pattern stuck on the right half of the display even though the display is unblanked. [how] Add a condition to not show the colour ramp test pattern when the display is unblanked. Signed-off-by:
Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by:
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Charlene Liu authored
[Description] port spdif fix to staging: spdif hardwired to afmt inst 1. spdif func pointer spdif resource allocation (reserve last audio endpoint for spdif only) Signed-off-by:
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Ahmad Othman authored
[Why] Video Timing Extended Metadata packet (VTEM) is not specific to freesync. So move it out of freesync module [How] - Moved VTEM from freesync module to info_packet module - Created new structure for VTEM parameters that can be used for VRR and FVA Signed-off-by:
Ahmad Othman <ahmad.othman@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Anthony Koo authored
Signed-off-by:
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Qingqing Zhuo authored
[Why] This function is not being used, it was left in when introducing DCN2 [How] Remove the function Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Martin Leung authored
[why] during a refactor a redundant code that has unknown behaviour was added. [how] removed old bad code Fixes: 8a31820b ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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Jaehyun Chung authored
[How] Allocate memory for default page and program memory block addr into default page addr register. Signed-off-by:
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Qingqing Zhuo authored
IEEE OUI will now be used while referring to certain vendors. instead of normal index Signed-off-by:
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Nikola Cornij authored
[why] Before a statically allocated PPS data structure, that did get zeroed-out at startup, had been re-used for making packed PPS SDP. With S3 fix, using a non-initialized PPS data structure was introduced, while wrongly assuming it'd get initialized before it's populated. As a consequence 'vbr_enable' and perhaps some other fields are left uninitialized when making packed PPS SDP. This can affect 'simple_422' as well because of the way PPS SDP packing is done (the fields are not masked first, only shifted). The behavior will be different, depending on the content of uninitialized data. [how] Zero-out PPS data structure at initialization time before it's populated Fixes: 1a9e3d45 ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end") Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Joseph Gravenor authored
add new function to get the voltage at the end of dcn_validate_bandwidth, to check against the highest voltage we allow. Created a stub to allow for optimizations Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
Sun peng Li <Sunpeng.Li@amd.com> Signed-off-by:
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Wyatt Wood authored
Adding NULL checks to various parameters in log_tf, to avoid nullptr errors Signed-off-by:
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Ilya Bakoulin authored
Set the writeback Hratio and Vratio in dml. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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