1. 25 Jul, 2011 1 commit
    • Tomoya MORINAGA's avatar
      pch_dma: Fix CTL register access issue · 0b052f4a
      Tomoya MORINAGA authored
      Currently, Mode-Control register is accessed by read-modify-write.
      
      According to DMA hardware specifications datasheet, prohibits this method.
      Because this register resets to 0 by DMA HW after DMA transfer completes.
      Thus, current read-modify-write processing can cause unexpected behavior.
      
      The datasheet says in case of writing Mode-Control register, set the value for only target channel, the others must set '11b'.
      e.g. Set DMA0=01b  DMA11=10b
      CTL0=33333331h
      CTL2=00002333h
      
      NOTE:
      CTL0 includes DMA0~7 Mode-Control register.
      CTL2 includes DMA8~11 Mode-Control register.
      
      This patch modifies the issue.
      Signed-off-by: default avatarTomoya MORINAGA <tomoya-linux@dsn.okisemi.com>
      Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
      0b052f4a
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