- 15 Sep, 2016 4 commits
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Jerome Brunet authored
Add EE domains pins for the i2c devices A,B,C Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com> Acked-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Jerome Brunet authored
Add EE domains pins for the NAND flash controller. Even tough we have no driver for the NAND flash controller yet, we need to have these pins in pinctrl as the actual pin are shared with the spifc controller. The bootloader on the S905-P200 setup pinmux for the NAND controller so we need the kernel to properly deactivate this if necessary. Acked-by:
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Arnd Bergmann authored
The newly added irqchip support for the stm32 pinctrl driver uses hierarchical IRQ domains as provided by the NVIC primary irqchip. This works great for any configuration that may be relevant on stm32, but when doing compile-testing (randconfig), we can enable it without NVIC or any other primary irqchip that enables IRQ_DOMAIN_HIERARCHY: drivers/pinctrl/stm32/pinctrl-stm32.c:212:13: error: 'irq_chip_eoi_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:213:20: error: 'irq_chip_mask_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:214:20: error: 'irq_chip_unmask_parent' undeclared here (not in a function) drivers/pinctrl/stm32/pinctrl-stm32.c:215:20: error: 'irq_chip_set_type_parent' undeclared here (not in a function) This adds a Kconfig dependency to limit compile-testing to configurations that have IRQ_DOMAIN_HIERARCHY already enabled. It's not obvious whether we should use 'depends on' or 'select' here, I think either one works, with 'depends on' being more intuitive, while 'select' would be less likely to cause dependency loops. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Fixes: 0eb9f683 ("pinctrl: Add IRQ support to STM32 gpios") Signed-off-by:
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Jerome Brunet authored
Add EE domains pins for the SPI flash controller Acked-by:
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- 14 Sep, 2016 4 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.9-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.9 (take three) - Return pinconf with arguments in packed format, - MSIOF and QSPI pin groups on R-Car V2H, - Voltage switching for SDHI on R-Car M2-W, E2, and M3-W.
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Simon Horman authored
All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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Simon Horman authored
All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by:
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Simon Horman authored
This follows the style of existing PORT_GP_X macros and will be used by a follow-up patch for the r8a7791 SoC. Signed-off-by:
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- 13 Sep, 2016 9 commits
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Alexandre TORGUE authored
"st,syscfg" entry was bad described. Signed-off-by:
Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by:
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Deepak authored
strict pin controller returns -EINVAL in case of pin request which is already claimed by somebody else. Following is the sequence of calling pin_request() from pinctrl_bind_pins():- pinctrl_bind_pins()->pinctrl_select_state()->pinmux_enable_setting()-> pin_request() But pinctrl_bind_pins() only returns -EPROBE_DEFER which makes device driver probe successful even if the pin request is rejected by the pin controller subsystem. This commit modifies pinctrl_bind_pins() to return error if the pin is rejected by pin control subsystem. Signed-off-by:
Deepak Das <deepak_das@mentor.com> [Rewrote to be cleaner] Signed-off-by:
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Martin Blumenstingl authored
This adds the SDIO interrupt pin which can be used by sd_emmc_a. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Suggested-by:
Neil Armstrong <narmstrong@baylibre.com> Fixes: 29885a65 ("pinctrl: meson-gxbb: add the pins for the SDIO/sd_emmc_a controller") Acked-by:
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Arnd Bergmann authored
The newly added aspeed driver tries to check for a negative return value from a pinctrl function, but stores the intermediate value in a 'bool' variable, which cannot work: drivers/pinctrl/aspeed/pinctrl-aspeed.c: In function 'aspeed_sig_expr_set': drivers/pinctrl/aspeed/pinctrl-aspeed.c:192:11: error: comparison of constant '0' with boolean expression is always false [-Werror=bool-compare] This slightly reworks the logic to use an explicit comparison with zero before assigning to the temporary variable. Reported-by:
Colin King <colin.king@canonical.com> Signed-off-by:
Joel Stanley <joel@jms.id.au> Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
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Julia Lawall authored
These structures are only used to copy into other structures, so declare them as const. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Julia Lawall authored
These structures are only used to copy into other structures, so declare them as const. The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; // </smpl> Signed-off-by:
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Agrawal, Nitesh-kumar authored
The earlier patch can be simplified by using a bool to indicate level trigger. Reviewed-by:
Pankaj Sen <Pankaj.Sen@amd.com> Signed-off-by:
Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> [Fixup to earlier manually applied patch] Signed-off-by:
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Alexandre TORGUE authored
This patch adds IRQ support to STM32 gpios. The EXTI controller has 16 lines dedicated to GPIOs. EXTI line n can be connected to only line n of one of the GPIO ports, for example EXTI0 can be connected to either PA0, or PB0, or PC0... This port selection is done by specifying the port number into System Config registers. Signed-off-by:
Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by:
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Alexandre TORGUE authored
Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 12 Sep, 2016 8 commits
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Vladimir Zapolskiy authored
If a GPIO controller description in board DTB contains information about mappings between GPIOs and pads under IOMUX control use it to request and free GPIOs with respect to pinctrl/pinmux subsystems. One of immediate positive functional changes is inability to request non-existing GPIOs, i.e. if there is no pad such. Also pinctrl/pinmux may now properly account pads occupied by requested GPIOs. The change has no effect, if "gpio-ranges" property is not found including the case if a board has no DTB firmware. Signed-off-by:
Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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Vladimir Zapolskiy authored
In general situation on-SoC GPIO controller drivers should be probed after pinctrl/pinmux controller driver, because on-SoC GPIOs utilize a pin/pad as a resource provided and controlled by pinctrl subsystem. This is stated in multiple places, e.g. from drivers/Makefile: GPIO must come after pinctrl as gpios may need to mux pins etc Looking at Freescale iMX SoC series specifics, imx*_pinctrl_init() functions are called at arch_initcall and postcore_initcall init levels, so the change of initcall level for gpio-mxc driver from postcore_initcall to subsys_initcall level is sufficient. Also note that the most of GPIO controller drivers settled at subsys_initcall level. If pinctrl subsystem manages pads with GPIO functions, the change is needed to avoid unwanted driver probe deferrals during kernel boot. Signed-off-by:
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Vladimir Zapolskiy authored
While only Freescale Vybrid SoC has settings of GPIO capabilities done by iomux controller, it is only a matter of GPIO controller driver implementation for the rest of Freescale/NXP SoCs from iMX series. As a practical example on GPIO request a pad function should be switched to GPIO, but because this requires updates to all particular iMX pinctrl drivers, for simplicity at the moment add only a proper connection between shared pinctrl-imx and pinctrl/pinmux core, namely .gpio_request_enable/.gpio_disable_free/.gpio_set_direction callbacks should return success to a caller. This change allows to progress by adding request/free callbacks into gpio-mxc.c driver. Signed-off-by:
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Marc Zyngier authored
at91 used to set a default trigger type for GPIO interrupts in order to cope with the old board files. These days are long gone, and it all gets probed through DT. Andras Szemzo reported that the Ethernet device on his board was bailing to be probed, due to a conflict in interrupt trigger. Surely enough, this is due to this default trigger still being present, and turning this into a IRQ_TYPE_NONE fixes the issue. Reported-by:
Andras Szemzo <szemzo.andras@gmail.com> Tested-by:
Marc Zyngier <marc.zyngier@arm.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Simon Horman authored
This patch supports the {get,set}_io_voltage operations of SDHI. This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v voltage switch. Based on work by Takeshi Kihara and Wolfram Sang. Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: -
Niklas Söderlund authored
The pinconf-generic code expects configurations with arguments to be returned in a packed format in order to be displayed properly by pinconf_generic_dump_one(). Reading /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins on r8a7795/salvator-x now shows: pin 101 (GP_3_5): output drive strength (9 mA), pin power source (3300 selector) Instead of: pin 101 (GP_3_5): output drive strength (0 mA), pin power source (0 selector) Signed-off-by:Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by:
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Sergei Shtylyov authored
Add MSIOF0/1 pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
Add QSPI pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by:
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- 07 Sep, 2016 11 commits
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Milo Kim authored
H3 has single PWM channel. The second PWM channel is not supported, so the pinctrl function should be removed. Signed-off-by:
Milo Kim <woogyom.kim@gmail.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Julia Lawall authored
Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by:
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Julia Lawall authored
Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by:
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Julia Lawall authored
Check for pinctrl_ops and pinmux_ops structures that are only stored in the pctlops field and the pmxops field, respectively, of a pinctrl_desc structure. These fields are declared const, so pinctrl_ops and pinmux_ops structures that have this property can be declared as const also. The semantic patch that makes this change in the pinctrl_ops is as follows. The pinmux_ops case is similar. (http://coccinelle.lip6.fr/) // <smpl> @r disable optional_qualifier@ identifier i; position p; @@ static struct pinctrl_ops i@p = { ... }; @ok@ identifier r.i; struct pinctrl_desc e; position p; @@ e.pctlops = &i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct pinctrl_ops e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct pinctrl_ops i = { ... }; // </smpl> Signed-off-by:
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Agrawal, Nitesh-kumar authored
In the function amd_gpio_irq_set_type, use the settings provided by the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure the GPIO registers. Ignore the settings from client. Reviewed-by:
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Mylène Josserand authored
Just like the other member of the sunxi family, let's add a pinctrl table for the muxing options. Signed-off-by:
Mylène Josserand <mylene.josserand@free-electrons.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by:
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Andrew Jeffery authored
A small subset of pins and functions are exposed. The selection of pins and functions is driven by the development of OpenBMC[1] on the AST2500 SoC, particularly around booting the IBM Witherspoon platform. [1] https://github.com/openbmc/docsSigned-off-by:
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Andrew Jeffery authored
A subset of the pins and functions are exposed. The selection of functions and pins is driven by the development of OpenBMC[1] on the AST2400 SoC, particularly around booting the OpenPOWER Palmetto development machine. [1] https://github.com/openbmc/docsSigned-off-by:
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Andrew Jeffery authored
The Aspeed SoCs typically provide more than 200 pins for GPIO and other functions. The signal enabled on a pin is determined on a priority basis, where a given pin can provide a number of different signal types. In addition to the priority levels, the Aspeed pin controllers describe the signal active on a pin by compound logical expressions involving multiple operators, registers and bits. Some difficulty arises as a pin's function bit masks for each priority level are frequently not the same (i.e. we cannot just flip a bit to change from a high to low priority signal), or even in the same register(s). Some configuration bits affect multiple pins, while in other cases the signals for a bus must each be enabled individually. Together, these features give rise to some complexity in the implementation. A more complete description of the complexities is provided in the associated header file. The patch doesn't implement pinctrl/pinmux/pinconf for any particular Aspeed SoC, rather it adds the framework for defining pinmux configurations. Signed-off-by:
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Andrew Jeffery authored
Outline expectations on the pin controller's relationship with the System Control Unit (SCU) IP through syscon, and document the compatible strings for 4th and 5th generation Aspeed SoC pin controllers. Signed-off-by:
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Martin Blumenstingl authored
sd_emmc_a is used a controller for the SDIO modules. This adds the pin configuration for the SDIO controller. Signed-off-by:
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- 05 Sep, 2016 3 commits
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Daniel Glöckner authored
It contains pin 50 instead of pin 40. Signed-off-by:
Daniel Glöckner <dg@emlix.com> Reviewed-by:
Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.9-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Add support for R-Car M3-W Add initial support for the Pin Function Controller on the Renesas R-Car M3-W SoC: - Basic definitions, - SCIF (serial) pins, groups and functions, - SDHI pins, groups and functions.
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Vladimir Zapolskiy authored
cat /sys/kernel/debug/pinctrl/${pinctrl}/pinconf-groups output is hardly readable, if a pin group contains more than one pin the output is glued and looks like this: MX6Q_PAD_SD1_DAT0: 0x17071MX6Q_PAD_SD1_CMD: 0x17071MX6Q_PAD_SD1_CLK: 0x17071 Add two space indentation and a new line separator to improve readability of the output. Signed-off-by:
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- 27 Aug, 2016 1 commit
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Paul Gortmaker authored
The Makefile currently controlling compilation of this code is: drivers/pinctrl/sirf/pinctrl-sirf.o --> drivers/pinctrl/sirf/Makefile:obj-y += pinctrl-sirf.o ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rongjun Ying <rongjun.ying@csr.com> Cc: Yuping Luo <yuping.luo@csr.com> Cc: Barry Song <baohua@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by:Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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