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- 05 Dec, 2018 1 commit
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Paul Kocialkowski authored
Add the description for the SRAM C1 section to the A64 device-tree. Since there is no entry for this section in the A64 manual, the base address and size were only verified to be consistent empirically. Signed-off-by:
Paul Kocialkowski <paul.kocialkowski@bootlin.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
Maxime Ripard <maxime.ripard@bootlin.com>
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- 23 Nov, 2018 1 commit
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Vasily Khoruzhick authored
Add nodes for i2s, digital and analog parts of audiocodec on A64. The routing paths listed are entries connecting the digital and analog side of the audio codec together. Due to how device tree works, these must be copied over to each board device tree, in addition to any board level routes. The oversampling rate is set to 128, so that when playing back 192 kHz audio samples, the MCLK runs at the same rate as the module clock, at 24.576 MHz. The user manual suggests using different oversampling rates for different sample rates, but that's not possible without a platform-specific machine driver. Signed-off-by:
Vasily Khoruzhick <anarsoul@gmail.com> [wens@csie.org: Lowered oversampling rate to 128; expanded commit message] Acked-by:
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- 20 Nov, 2018 1 commit
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Jagan Teki authored
Add support for Allwinner A64 has Mali-400MP2. All interrupt lines are mentioned in the manual so used the same. Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Signed-off-by:
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- 25 Sep, 2018 1 commit
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Jagan Teki authored
Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first TCON is connected to LCD and the second is to HDMI. The HDMI controller/PHY pair is similar to the one on H3/H5. Add all required device tree nodes of the display pipeline, including the TCON0 LCD one and the TCON1 HDMI one. Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Signed-off-by:
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- 03 Sep, 2018 3 commits
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Chen-Yu Tsai authored
The pinmux name and label for a specific function should denote which pingroup it is on, or if there is only one option for the function, have not enumerating prefix/suffix at all. The "r_i2c_pins_a" label is renamed to "r_i2c_pl89_pins" to fit our current style. The node name "i2c" is also changed to "r-i2c-pl89-pins" to match. The reason for the peculiar name is that the other option for muxing R_I2C is on the PL0/PL1 pins, so the name has to mention the pin numbers in addition to the pingroup. Acked-by:
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Chen-Yu Tsai authored
The pinmux name and label for a specific function should denote which pingroup it is on, or if there is only one option for the function, have not enumerating prefix/suffix at all. The "uart0_pins_a" label is renamed to "uart0_pb_pins" to fit our current style. The node name "uart0" is also changed to "uart0-pb-pins" to match. Acked-by:
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Chen-Yu Tsai authored
The eMMC 5.0 standard introduced the data strobe (DS) pin. This pin is not used for pre-5.0 data modes, nor is it found on pre-5.0 eMMC chips. On the A64, this pin is muxed with spi0's MISO pin. If the DS pin is included in the mmc2 pinmux by default, this wil prevent the usage of both mmc2 and spi0 together. Instead, split out the DS pin to a separate pinmux that only gets used by boards that actually have it wired up. Currently supported ones include the Bananapi M64 and Pine64 Pinebook. These are fixed up. Fixes: a3e8f492 ("arm64: allwinner: a64: Add MMC pinctrl nodes") Fixes: b8bcf0e1 ("arm64: allwinner: add BananaPi-M64 support") Fixes: df35fbcf ("arm64: dts: allwinner: add support for Pinebook") Acked-by:
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- 27 Aug, 2018 2 commits
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Andre Przywara authored
Current kernels complain when booting on an A64 Soc: .... [ 1.904297] cacheinfo: Unable to detect cache hierarchy for CPU 0 .... Not a real biggie on this flat topology, but also easy enough to fix. Add the L2 cache node and let each CPU point to it. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Acked-by:
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Emmanuel Vadot authored
The A64 have a SID controller which consist of EFUSE (starting at 0x200) and three registers to read/write some of the protected efuses. Signed-off-by:
Emmanuel Vadot <manu@freebsd.org> Signed-off-by:
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- 19 Jul, 2018 1 commit
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Corentin Labbe authored
address-cells/size-cells is unnecessary for dwmac-sun8i node. It was in early days, but since a mdio node is used, it could be removed. This patch fix the following DT warning: Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by:
Corentin Labbe <clabbe@baylibre.com> Signed-off-by:
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- 27 Jun, 2018 2 commits
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Icenowy Zheng authored
As the U-Boot bootloader now is also capable of initialize the HDMI on A64 boards, add a simplefb device tree node for accessing the HDMI framebuffer initialized by the bootloader. Signed-off-by:
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Icenowy Zheng authored
As we have all necessary parts to enable the DE2 CCU on the Allwinner A64 SoC, add the needed device tree nodes, including the DE2 CCU itself and the DE2 bus. The "mixer0-lcd0" simplefb device node is updated to use the DE2 CCU. Signed-off-by:
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- 19 Jun, 2018 1 commit
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Icenowy Zheng authored
Allwinner A64 has a SRAM controller, and in the device tree currently we have a syscon node to enable EMAC driver to access the EMAC clock register. As SRAM controller driver can now export regmap for this register, replace the syscon node to the SRAM controller device node, and let EMAC driver to acquire its EMAC clock regmap. Signed-off-by:
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- 18 Jun, 2018 3 commits
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Andre Przywara authored
The Allwinner A64 SoC features two PWM controllers, which are fully compatible to the one used in the A13 and H3 chips. Add the nodes for the devices (one for the "normal" PWM, the other for the one in the CPUS domain) and the pins their outputs are connected to. On the A64 the "normal" PWM is muxed together with one of the MDIO pins used to communicate with the Ethernet PHY, so it won't be usable on many boards. But the Pinebook laptop uses this pin for controlling the LCD backlight. On Pine64 the CPUS PWM pin however is routed to the "RPi2" header, at the same location as the PWM pin on the RaspberryPi. Tested on Pinebook and Teres-I [vasily: fixed comment message as requested by Stefan Bruens, added default muxing options to pwm and r_pwm nodes] Signed-off-by:Harald Geyer <harald@ccbib.org> Signed-off-by:
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Icenowy Zheng authored
Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has two groups of pinmuxes on PL bank, so it's called R_I2C. Add support for this I2C controller and the pinmux which doesn't conflict with RSB. Signed-off-by:
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Jagan Teki authored
Outside of SOC few chips need external clock source through RTC example Wifi chip. So RTC clock nodes to phandle 32kHz external oscillator. prefix rtc- with clock-output-names defined in dt-binding to avoid confusion with existing osc32k name. Signed-off-by:
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- 19 Mar, 2018 3 commits
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Harald Geyer authored
The A64 SoC features two display pipelines, one has a LCD output, the other has a HDMI output. Add support for simplefb for the LCD output. Tested on Teres I. This patch was inspired by work of Icenowy Zheng. Signed-off-by:
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Harald Geyer authored
Add a watchdog node for the A64, automatically enabled on all boards. Since the device is compatible with an existing driver, we only reserve a new compatible string to be used together with the fall back. Tested on Olimex Teres-I. Signed-off-by:
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Harald Geyer authored
Add the proper pin group node to reference in board files. Reviewed-by:
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- 14 Feb, 2018 3 commits
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Marcus Cooper authored
Add the DAI blocks to the device tree. I2S0 and I2S1 are for connecting to an external codec. Signed-off-by:
Marcus Cooper <codekipper@gmail.com> Signed-off-by:
Maxime Ripard <maxime.ripard@free-electrons.com>
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Marcus Cooper authored
Add the device tree sound bindings for the S/PDIF block. Signed-off-by:
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Marcus Cooper authored
Add the SPDIF transceiver controller block and pin to the A64 dtsi. Signed-off-by:
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- 31 Oct, 2017 2 commits
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Corentin Labbe authored
stmmac bindings docs said that its mdio node must have compatible = "snps,dwmac-mdio"; Since dwmac-sun8i does not have any good reasons to not doing it, all their MDIO node must have it. Signed-off-by:
Corentin Labbe <clabbe.montjoie@gmail.com> Acked-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Corentin Labbe authored
The original dwmac-sun8i DT bindings have some issue on how to handle integrated PHY and was reverted in last RC of 4.13. But now we have a solution so we need to get back that was reverted. This patch restore arm64 DT about dwmac-sun8i for A64 This reverts commit 87e1f5e8 ("arm64: dts: allwinner: Revert EMAC changes") Signed-off-by:
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- 19 Oct, 2017 1 commit
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Rob Herring authored
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm64/boot/dts -type -f -name '*.dts*' Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 28 Sep, 2017 2 commits
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Stefan Brüns authored
The spi controller nodes omit the dma controller/channel references, add it. This does not yet enable DMA for SPI transfers, as the spi-sun6i driver lacks support for DMA, but always uses PIO to the FIFO. Signed-off-by:
Stefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by:
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Stefan Brüns authored
The A64 SoC has a DMA controller that supports 8 DMA channels to and from various peripherals. The last used DRQ port is 27. Add a device node for it. Signed-off-by:
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- 27 Sep, 2017 2 commits
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Corentin LABBE authored
This patch fix the warning "xxx has a unit name, but no reg property" by removing "@0" from such node Signed-off-by:
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Corentin LABBE authored
This patch remove leading 0 of unit address and so remove lots of warning when building DT with W=1. Signed-off-by:
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- 17 Sep, 2017 1 commit
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Stefan Brüns authored
The A64 SPI controllers are register compatible to the h3/h5 SPI controllers. The A64 has two SPI controllers, each with a single chip select. The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted, as the A64 DMA support is currently missing. Signed-off-by:
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- 28 Aug, 2017 1 commit
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Maxime Ripard authored
Since the discussion is not settled yet for the EMAC, and that the release in getting really close, let's revert the changes for now, and we'll reintroduce them later. Acked-by:
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- 27 Jul, 2017 1 commit
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Corentin Labbe authored
The datasheet said that emac register size is 0x10000 not 0x100 Signed-off-by:
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- 17 Jul, 2017 1 commit
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Icenowy Zheng authored
Allwinner A64 SoC features a R_INTC controller, which controls the NMI line, and this interrupt line is usually connected to the AXP PMIC. Add support for it. Signed-off-by:
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- 01 Jul, 2017 1 commit
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Maxime Ripard authored
This reverts commits 2c0cba48 ("arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module") to 2428fd0f ("arm64: defconfig: Enable dwmac-sun8i driver on defconfig") and 3432a86e ("arm: sun8i: orangepipc: use internal phy-mode") to 5a79b4f2 ("arm: sun8i: orangepi-2: use internal phy-mode") that should be merged through the arm-soc tree, and end up in merge conflicts and build failures. Signed-off-by:
David S. Miller <davem@davemloft.net>
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- 07 Jun, 2017 6 commits
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Corentin Labbe authored
The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit connections. It is very similar to the device found in the Allwinner H3, but lacks the internal 100 Mbit PHY and its associated control bits. This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps it disabled at this level. Signed-off-by:
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Corentin Labbe authored
This patch add the dt node for the syscon register present on the Allwinner A64. Only two register are present in this syscon and the only one useful is the one dedicated to EMAC clock. Signed-off-by:
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Chen-Yu Tsai authored
The A64 device tree file has some remnants of raw number references to the CCU node, likely from when the CCU bindings and device tree changes were first merged. Convert these, and the R_CCU ones, to use the proper defined macros from their respective device tree binding header files. Signed-off-by:
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Andreas Färber authored
Pine64 exposes all A64 UARTs, not just UART0. Since the pins can be used as GPIO, don't enable the new UART nodes by default, but prepare the pinctrl settings to aid in activating them via overlays, i.e., overriding the status property of &uartX nodes. For UART4 (Euler) the safer route of not including RTS/CTS pins is chosen, whereas for UART1 (Bluetooth) they are included. Add the corresponding pinctrl nodes where missing. Suggested-by:
Andreas Färber <afaerber@suse.de> Signed-off-by:
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Icenowy Zheng authored
Allwinner A64 have a RSB controller like the one on A23/A33 SoCs. Add it and its pinmux. Signed-off-by:
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Andreas Färber authored
UART2 is exposed on the Pi connector of Pine64. Make a pinctrl node available at the SoC level, to simplify enabling UART2 via DT overlay. Signed-off-by:
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