- 04 Jun, 2023 12 commits
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Kuogee Hsieh authored
DPU < 7.0.0 has DPU_PINGPONG_DSC feature bit set to indicate it requires both dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() to be executed to complete DSC configuration if DSC hardware block is present. Hence test DPU_PINGPONG_DSC feature bit and assign DSC related functions to the ops of PINGPONG block accordingly if DPU_PINGPONG_DSC bit is set. Changes in v6: -- split patches, this patch has function handles DPU_PINGPONG_DSC bit Changes in v9: -- the original code of assigning dsc related functions to the ops of pingpong block without testing the DPU_PINGPONG_DSC feature bit was restored back due to rebase error which defeat the purpose of this patch. Remove those error code. Changes in v10: -- change commit title -- correct texts at changes in v9 Changes in v12: -- fixed length too long at Changes in v9 Signed-off-by:Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/539504/ Link: https://lore.kernel.org/r/1685036458-22683-5-git-send-email-quic_khsieh@quicinc.comSigned-off-by:
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Kuogee Hsieh authored
DPU < 7.0.0 requires the PINGPONG block to be involved during DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC encoder engine was moved to INTF with the help of the flush mechanism. Add a DPU_PINGPONG_DSC feature bit to restrict the availability of dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() on the PINGPONG block to DPU < 7.0.0 hardware, as the registers are not available on DPU 7.0.0 and higher anymore. Add DPU_PINGPONG_DSC to PINGPONG_SDM845_MASK, PINGPONG_SDM845_TE2_MASK and PINGPONG_SM8150_MASK which is used for all DPU < 7.0 chipsets. changes in v6: -- split patches and rearrange to keep catalog related files at this patch changes in v7: -- rewording commit text as suggested at review comments changes in v9: -- delete BIT(DPU_PINGPONG_DSC) from PINGPONG_SDM845_TE2_MASK changes in v10: -- correct order of commit text Signed-off-by: -
Kuogee Hsieh authored
The CTL_FLUSH register should be programmed with the 22th bit (DSC_IDX) to flush the DSC hardware blocks, not the literal value of 22 (which corresponds to flushing VIG1, VIG2 and RGB1 instead). Changes in V12: -- split this patch out of "separate DSC flush update out of interface" Changes in V13: -- rewording the commit text Changes in V14: -- drop 'DSC" from "The DSC CTL_FLUSH register" at commit text Fixes: 77f6da90 ("drm/msm/disp/dpu1: Add DSC support in hw_ctl") Signed-off-by:
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Dmitry Baryshkov authored
Rework SSPP and WB code to use common helper for programming QoS settings. Reviewed-by:
Jeykumar Sankaran <quic_jeykumar@quicinc.com> Signed-off-by:
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Dmitry Baryshkov authored
Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field, drop the structure and use corresponding bool directly. Reviewed-by:
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Dmitry Baryshkov authored
This flag is always passed to _dpu_plane_set_qos_ctrl(), so drop it and remove corresponding conditions from the mentioned function. Reviewed-by:
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Dmitry Baryshkov authored
After removal of DPU_PLANE_QOS_VBLANK_CTRL, several fields of struct dpu_hw_pipe_qos_cfg are fixed to false/0. Drop them from the structure (and drop the corresponding code from the functions). The DPU_PLANE_QOS_VBLANK_AMORTIZE flag is also removed, since it is now a NOP. Reviewed-by:
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Dmitry Baryshkov authored
Drop support for DPU_PLANE_QOS_VBLANK_CTRL flag. It is not used both in upstream driver and in vendor SDE driver. Reviewed-by:
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Dmitry Baryshkov authored
Slightly rearrainge code in dpu_plane_sspp_update_pipe() to group QoS/LUT related functions. Reviewed-by:
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Dmitry Baryshkov authored
The function dpu_plane_sspp_update_pipe() contains code to skip enabling the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845 repurpose DMA SSPP for the cursor planes because they lack the real CURSOR SSPP. Fix the condition to actually check that the plane is CURSOR or not. Reviewed-by:
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Dmitry Baryshkov authored
Get rid of intermediatory configuration structure and defines. Pass the format and the enablement bit directly to the new helper. The WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP and WB CDP settings. Reviewed-by:
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Dmitry Baryshkov authored
Reorder SSPP register definitions to sort them in the ascending order. Move register bitfields after the register definitions. Signed-off-by:
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- 22 May, 2023 28 commits
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Dmitry Baryshkov authored
Move the check for lm->pingpong being not NONE from dpu_rm_init() to dpu_lm_init(), following the change to dpu_hw_intf_init(). Suggested-by:
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Dmitry Baryshkov authored
On msm8998/sdm845 some LM blocks do not have corresponding PINGPONG block. Currently the driver uses PINGPONG_MAX for such cases. Switch that to use PINGPONG_NONE instead, which is more logical. Reviewed-by:
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Dmitry Baryshkov authored
dpu_rm_init() contains checks for block->id values. These were logical in the vendor driver, when one can not be sure which values were passed from DT. In the upstream driver this is not necessary: the catalog is a part of the driver, we control specified IDs. Suggested-by:
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Dmitry Baryshkov authored
Using IS_ERR_OR_NULL() together with PTR_ERR() is a typical mistake. If the value is NULL, then the function will return 0 instead of a proper return code. Moreover dpu_hw_dsc_init() can not return NULL. Replace the IS_ERR_OR_NULL() call with IS_ERR(). This follows the commit 740828c7 ("drm/msm/dpu: fix error handling in dpu_rm_init"), which removed IS_ERR_OR_NULL() from RM init code, but then the commit f2803ee9 ("drm/msm/disp/dpu1: Add DSC support in RM") added it for DSC init. Suggested-by:
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Konrad Dybcio authored
DPU5 and newer targets enable this unconditionally. Move it from the SC7280 mask to the SC7180 one. Fixes: 7e6ee553 ("drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target") Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/538159/ Link: https://lore.kernel.org/r/20230508-topic-hctl_en-v2-1-e7bea9f1f5dd@linaro.org [DB: removed BIT(DPU_INTF_DATA_COMPRESS), which is not yet merged] Signed-off-by:
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Dmitry Baryshkov authored
Stop using _sspp_subblk_offset() to get offset of the csc_blk. Inline this function and use ctx->cap->sblk->csc_blk.base directly. As this was the last user, drop _sspp_subblk_offset() too. Reviewed-by:
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Dmitry Baryshkov authored
Stop using _sspp_subblk_offset() to get offset of the scaler_blk. Inline this function and use ctx->cap->sblk->scaler_blk.base directly. Reviewed-by:
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Dmitry Baryshkov authored
The src_blk declares a lame copy of main SSPP register space. It's offset is always 0. It's length has been fixed to 0x150, while SSPP's length is now correct. Drop the src_blk and access SSPP registers without additional subblock lookup. Signed-off-by:
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Marijn Suijten authored
Now that newer DPU platforms use a readpointer-done interrupt on the INTF block, stop providing the unused interrupt on the PINGPONG block. Signed-off-by:
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Marijn Suijten authored
Since DPU 5.0.0 the TEARCHECK registers and interrupts moved out of the PINGPONG block and into the INTF. Implement the necessary callbacks in the INTF block, and use these callbacks together with the INTF_TEAR interrupts. Signed-off-by:
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Marijn Suijten authored
These functions are always called consecutively and are best bundled together for simplicity, especially when the same structure of callbacks will be replicated later on the interface block for INTF TE support. The enable_tearcheck(false) case is now replaced with a more obvious disable_tearcheck(), encapsulating the original register write with 0. Suggested-by:
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Marijn Suijten authored
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of the PINGPONG block and into the INTF block. The new interrupts are described in dpu_hw_interrupts.c, now wire them up in individual SoC catalog files by setting the intr_tear_rd_ptr to the IRQ index spcified in the offset table and enabling this set of DPU interrupts via the mdss_irqs bitmask. Signed-off-by:
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Marijn Suijten authored
All SoCs since DPU 5.0.0 have the tear interrupt registers moved out of the PINGPONG block and into the INTF block. Wire up the IRQ register masks in the interrupt table for enabling, reading and clearing them. Signed-off-by:
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Marijn Suijten authored
As the INTF block is going to attain more interrupts that don't share the same MDP_SSPP_TOP0_INTR register, factor out the _reg argument for the caller to construct the right interrupt index (register and bit index) to not make the interrupt bit arguments depend on one of multiple interrupt register indices. This brings us more in line with how PP_BLK specifies its interrupts and allows for better wrapping in the arrays. Signed-off-by:
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Konrad Dybcio authored
Now that newer SoCs since DPU 5.0.0 manage tearcheck in the INTF instead of PINGPONG block, move the struct definition to a common file. Also, bring in documentation from msm-4.19 techpack while at it. Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> [Marijn: Also move dpu_hw_pp_vsync_info] Signed-off-by:
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Marijn Suijten authored
Since hardware revision 5.0.0 the TE configuration moved out of the PINGPONG block into the INTF block, including vsync source selection that was previously part of MDP top. Writing to the MDP_VSYNC_SEL register has no effect anymore and is omitted downstream via the DPU/SDE_MDP_VSYNC_SEL feature flag. This flag is only added to INTF blocks used by hardware prior to 5.0.0. The code that writes to these registers in the INTF block will follow in subsequent patches. Signed-off-by:
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Marijn Suijten authored
Since hardware revision 5.0.0 the TE configuration moved out of the PINGPONG block into the INTF block. Writing these registers has no effect, and is omitted downstream via the DPU/SDE_PINGPONG_TE feature flag. This flag is only added to PINGPONG blocks used by hardware prior to 5.0.0. The existing PP_BLK_TE macro has been removed in favour of directly passing this feature flag, which has thus far been the only difference with PP_BLK. PP_BLK_DITHER has been left in place as its embedded feature flag already excludes this DPU_PINGPONG_TE bit and differs by setting the block length to zero, as it only contains a DITHER subblock. The code that writes to these registers in the INTF block will follow in subsequent patches. Signed-off-by:
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Marijn Suijten authored
This autorefresh disable logic in the physical command-mode encoder consumes three callbacks to the pingpong block, and will explode in unnecessary complexity when the same callbacks need to be called on the interface block instead to accommodate INTF TE support. To clean this up, move the logic into the pingpong block under a disable_autorefresh callback, replacing the aforementioned three get_autorefresh, setup_autorefresh and get_vsync_info callbacks. The same logic will have to be replicated to the interface block when it receives INTF TE support, but it is less complex than constantly switching on a "has_intf_te" boolean to choose a callback. Suggested-by:
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Marijn Suijten authored
This callback was migrated from downstream when DPU1 was first introduced to mainline, but never used by any component. Drop it to save some lines and unnecessary confusion. Suggested-by:
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Marijn Suijten authored
Instead of hardcoding many register defines for every INTF and AD4 index with a fixed stride, turn the defines into singular chunks of math that compute the address using the base and this fixed stride multiplied by the index given as argument to the definitions. MDP_SSPP_TOP0_OFF is dropped as that constant is zero anyway, and all register offsets related to it live in dpu_hwio.h. Suggested-by:
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Marijn Suijten authored
A bunch of registers were appended at the end in e.g. commit 91143873 ("drm/msm/dpu: Add MISR register support for interface") rather than being inserted in a place that maintains numerical sorting: restore said numerical sorting. Signed-off-by:
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Marijn Suijten authored
A bunch of registers are indented with two extra spaces, looking as if these are values corresponding to the previous register which is not the case, rather these are simply also register offsets and should only have a single space separating them and the #define keyword. Signed-off-by:
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Marijn Suijten authored
According to various downstream sources the PCC sub-block inside DSPP is version 4.0 since DPU 4.0 and higher, including SC7[12]80 at DPU version 6.2 and 7.2 respectively. After correcting the version this struct becomes identical to sm8150_dspp_sblk which is used all across the catalog: replace uses of sc7180_dspp_sblk with that and remove the struct definition for sc7180_dspp_sblk entirely. Fixes: 4259ff7a ("drm/msm/dpu: add support for pcc color block in dpu driver") Signed-off-by:
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Abhinav Kumar authored
Add writeback support for sc7280. This was validated with kms_writeback test case in IGT. Signed-off-by:
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Dmitry Baryshkov authored
The driver doesn't support hsic/memcolor and pcc SSPP subblocks. Drop corresponding definitions. Signed-off-by:
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Abhinav Kumar authored
Since GC and IGC masks have now been dropped, DSPP_MSM8998_MASK is the same as DSPP_SC7180_MASK. Since DSPP_SC7180_MASK is used more than DSPP_MSM8998_MASK, lets drop the latter. Signed-off-by:
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Abhinav Kumar authored
Gamma Correction (GC) and Inverse Gamma Correction(IGC) is currently unused. In addition dpu_dspp_sub_blks didn't even have an igc member describing the block. Drop related code from the dpu hardware catalog otherwise this becomes a burden to carry across chipsets in the catalog. changes in v3: - drop IGC related code from dpu_hw_catalog too - update commit text accordingly Signed-off-by:
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Abhinav Kumar authored
Inverse gamma correction blocks (IGC) are not used today so lets remove the usage of DPU_DSPP_IGC in the DSPP flush to make it easier to remove IGC from the catalog. We can add this back when IGC is properly supported in DPU with one of the standard DRM properties. changes in v3: - minor change dspp -> DSPP in commit text Signed-off-by:
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