- 07 Sep, 2021 4 commits
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Jani Nikula authored
Avoid extra caching of the data. v2: Check for !info->devdata in intel_bios_port_aux_ch() (Ankit) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b1b9f0032b353c3279b4546d6acdb696fe0b6136.1630512523.git.jani.nikula@intel.com
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Jani Nikula authored
Avoid extra caching of the data. Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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Jani Nikula authored
Avoid extra caching of the data. Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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Jani Nikula authored
Avoid extra caching of the data. Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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- 02 Sep, 2021 8 commits
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Animesh Manna authored
Added HBR3 support for ADL_P and ADL_S platform. Bspec: 53597, 53720, 49185, 55409 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Jani Nikula authored
Combo phy is limited to 5.4 GHz on low-voltage SKUs, but both eDP and DP can do 8.1 GHz on combo phy. Bspec: 49182, 49205, 49202 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Animesh Manna authored
Only higher voltage sku can support HBR3 so a condition check added in max source rate calculation for ehl/jsl. Bspec: 32247, 20598 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Jani Nikula authored
Combo phy is limited to 5.4 GHz on low-voltage SKUs. Combo phy DP is limited to 5.4 GHz, while combo phy eDP can do 8.1 GHz. Bspec: 20584, 20598, 49180, 49201 Cc: Imre Deak <imre.deak@intel.com> Signed-off-by:
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Matt Atwood authored
intel_dp_set_source_rates() calls intel_dp_is_edp(), which is unsafe to use before intel_encoder->type is set. This causes incorrect max source rate to be used for display 11+. On EHL and JSL, HBR3 is used instead of HBR2, and on the other affected platforms, HBR2 is used instead of HBR3. Move intel_dp_set_source_rates() to after intel_encoder->type is set. Add comment to intel_dp_is_edp() describing unsafe usages. Cleanup intel_dp_init_connector() while at it. Note: The same change was originally added as commit 680c45c7 ("drm/i915/dp: Correctly advertise HBR3 for GEN11+"), but later reverted due to issues in CI in commit d3913019 ("Revert "drm/i915/dp: Correctly advertise HBR3 for GEN11+""). Cc: Uma Shankar <uma.shankar@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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Jani Nikula authored
Clean up the LPSP capability printout. No functional changes. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Jani Nikula authored
Clean up the LPSP status printout. No functional changes. Reviewed-by:
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Jani Nikula authored
Accidentally dropped the else in a rebase fail, causing the DG2 max rate to be overwritten later in the if ladder. Fixes: e752d1f9 ("drm/i915/dg2: add DG2 UHBR source rates") Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
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- 01 Sep, 2021 3 commits
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Vandita Kulkarni authored
Enable MIPI DSI support on ADL-P platform. The esc clock changes, WA changes are taken care in the previous patches. As per the Bspec the seq remains to be same as TGL. Signed-off-by:
Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
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Vandita Kulkarni authored
Wa_16012360555 SW will have to program the "LP to HS Wakeup Guardband" field to account for the repeaters on the HS Request/Ready PPI signaling between the Display engine and the DPHY. v2: Fix build issue. v3: Align to new naming (Jani) Signed-off-by:
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Vandita Kulkarni authored
Xelpd supports larger small joiner ram. Signed-off-by:
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- 30 Aug, 2021 5 commits
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José Roberto de Souza authored
We had a mix of intel_edp_drrs_*(), intel_dp_drrs_*() and intel_dp_set_drrs_state(), so properly renaming all functions to keep the same pattern. While at it, also dropping intel_dp_set_drrs_state from the documentation as it is a static function. v3: - dropping documentation style comment in static function (intel_drrs_set_state) Reviewed-by:
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José Roberto de Souza authored
intel_dp.c is a 5k lines monster, so moving DRRS out of it to reduce some lines from it. Reviewed-by:
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José Roberto de Souza authored
At this point is sure that HSW and BDW will never have PSR enabled by default, so here dropping it from device info and cleaning up code. v2: - enable psr support for display 9 Reviewed-by:
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Animesh Manna authored
UHBR modes has higher link rate and added new values for programming mpll of SNPS phy. No change in sequence, only the pll parameters are different for UHBR modes. Reviewed-by:
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Jani Nikula authored
Apparently the last reader of i915->active_pipes was removed with commit ef79d62b ("drm/i915: Encapsulate dbuf state handling harder"), and now it's only ever written to. Remove it completely. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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- 27 Aug, 2021 5 commits
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Jani Nikula authored
These shouldn't happen, but in the off chance they do, we'll want a warning rather than panic. Reviewed-by:
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Jani Nikula authored
This fairly detailed stuff that really has no place in intel_display.c. Combine the calls into one to avoid exposing both. Reviewed-by:
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Jani Nikula authored
Accept slight duplication in the fdi link train hooks in exchange for simplification in ilk_pch_enable(). This lets us make ivb_update_fdi_bc_bifurcation() static again, now in intel_fdi.c. Reviewed-by:
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Jani Nikula authored
Move FDI related functions to intel_fdi.c. Don't bother with renaming as we'll make the functions static shortly. Reviewed-by:
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Jani Nikula authored
Move FDI related functions to intel_fdi.c. Rename to have intel_fdi prefix while at it. Reviewed-by:
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- 26 Aug, 2021 5 commits
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Rodrigo Vivi authored
Merge tag 'drm-misc-intel-oob-hotplug-v1' of git://git.kernel.org/pub/scm/linux/kernel/git/hansg/linux into drm-intel-next Topic branch for drm-misc / drm-intel for OOB hotplug support for Type-C connectors Signed-off-by:
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Jani Nikula authored
The tables should be const arrays of const pointers, not just arrays of const pointers. Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
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Jani Nikula authored
Follow the usual naming conventions. Also pull HAS_GMCH() check to intel_panel_fitting(). No functional changes. Cc: Lyude Paul <lyude@redhat.com> Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Jani Nikula authored
Follow the usual naming conventions. As a drive-by cleanup, also pass intel_connector instead of drm_connector to intel_backlight_setup(). No functional changes. Cc: Lyude Paul <lyude@redhat.com> Reviewed-by:
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Jani Nikula authored
In a long overdue refactoring, split out backlight code to new intel_backlight.[ch]. Simple code movement, leave renames for follow-up work. No functional changes. Cc: Lyude Paul <lyude@redhat.com> Reviewed-by:
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- 25 Aug, 2021 10 commits
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Matt Roper authored
The memory latency values returned by pcode on DG2 are in units of "2 usec" rather than 1 usec on all other platforms. I.e., we need to double the value returned by pcode to obtain the true latency value. The bspec wording here was a bit ambiguous as to whether it wanted us to multiply or divide the pcode value by two, but we confirmed offline with the hardware team that we need to double the value the pcode gives us; this change is intended to support a larger range of potential latency values. Bspec: 49326 Signed-off-by:
Harish Chegondi <harish.chegondi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210820225710.401136-1-matthew.d.roper@intel.com
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Ville Syrjälä authored
intel_prepare_shared_dpll() is now useless, so get rid of it. Signed-off-by:
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Ville Syrjälä authored
Move the FP divider programming into ibx_pch_dpll_enable(). No reason that I can see why these would have to be programmed this early. Signed-off-by:
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Ville Syrjälä authored
Can't think of a good reason why we'd need to program the FP dividers so early. Let's just do it when programming the rest of the DPLL. Signed-off-by:
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Ville Syrjälä authored
Use ilk_needs_fb_cb_tune() for reduced_clock instead of hand rolling it. Also ilk_needs_fb_cb_tune() can just use the precomputed M value instead of calculating it again. Signed-off-by:
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Ville Syrjälä authored
We always call the vlv/chv prepare_pll() just before enable_pll(). Move the calls into the enable_pll() funcs. We can also consolidate the DPLL_VCO_ENABLE checks while at it. Signed-off-by:
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Ville Syrjälä authored
On g4x and pch the DPLL has two P1 dividers (for refresh rate switching). Program the FPx1 P1 divider consistently to the reduced clock P1 divider if available, otherwise just program it to the same value as the FPx0 P1 divider. Signed-off-by:
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Ville Syrjälä authored
Get rid of the local 'reg' variable for the DPLL control register in i9xx_enable_pll(). We have other registers in there too so this is just making things more confusing. Signed-off-by:
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Ville Syrjälä authored
s/pipe_config/crtc_state/ in the DPLL code. Signed-off-by:
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Ville Syrjälä authored
Stop passing both the crtc and its state to the DPLL functions. The state alone is enough. Signed-off-by:
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