- 22 Apr, 2022 18 commits
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Srinivasa Rao Mandadapu authored
Add pin control support for SC7280 LPASS LPI. Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Co-developed-by:
Venkata Prasad Potturu <quic_potturu@quicinc.com> Signed-off-by:
Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1650285427-19752-7-git-send-email-quic_srivasam@quicinc.comSigned-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Srinivasa Rao Mandadapu authored
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver to allow reusing the common code in the addition of subsequent platforms. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Update custom pin group structure members with framework generic group_desc structure and replace the driver's custom pinctrl_ops with framework provided generic pin control group functions to avoid redundant code written in lpass lpi driver. Signed-off-by:
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Srinivasa Rao Mandadapu authored
Update NO_SLEW macro to LPI_NO_SLEW macro as this driver lpi specific. Signed-off-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1650285427-19752-4-git-send-email-quic_srivasam@quicinc.comSigned-off-by:
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Srinivasa Rao Mandadapu authored
Add device tree binding Documentation details for Qualcomm SC7280 LPASS LPI pinctrl driver. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Srinivasa Rao Mandadapu authored
Change generic lpass lpi pincotrol bindings file to SoC specific file, to distinguish and accomadate other SoC specific dt bindings. Signed-off-by:
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Sebastian Reichel authored
Add compatible string for rk3588 pin controller. No other changes are required, since the new controller can use the old binding. Signed-off-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220422170920.401914-12-sebastian.reichel@collabora.comSigned-off-by:
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Linus Walleij authored
The MC2 MMC interface can be configured with the FBCLK (feedback clock) unconnected, leaving the pin available for reuse for something else. Add a group mc2_a_2 for this. Signed-off-by:
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Lv Ruyi authored
Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately.Make the code simpler without functional changes. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Lv Ruyi <lv.ruyi@zte.com.cn> Link: https://lore.kernel.org/r/20220418020238.2556989-1-lv.ruyi@zte.com.cnSigned-off-by:
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Paul Cercueil authored
By being a bit smarter about how the SoC version checks are performed, it is possible to have all the code paths that correspond to SoCs disabled in the kernel config automatically marked as dead code by the compiler, and therefore garbage-collected. With this patch, when compiling a kernel that only targets the JZ4760 for instance, the driver is now about 4.5 KiB smaller. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220412162218.32509-1-paul@crapouillou.netSigned-off-by:
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Johan Jonker authored
Add the compatible string "rockchip,rk3036-pinctrl" in already in use in rk3036.dtsi to rockchip,pinctrl.yaml. Signed-off-by:
Johan Jonker <jbx6244@gmail.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
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Alexander Stein authored
Convert the i.MX7D pinctrl binding to DT schema format using json-schema Signed-off-by:
Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220303150653.1903910-1-alexander.stein@ew.tq-group.comSigned-off-by:
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Krzysztof Kozlowski authored
The MODULE_DEVICE_TABLE already creates proper alias for platform driver. Having another MODULE_ALIAS causes the alias to be duplicated. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407202509.23228-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Qianggui Song authored
The kernel test robot reported a warning as below: >> drivers/pinctrl/meson/pinctrl-meson-s4.c:178:27: warning: unused variable 'tdm_sclk1_c_pins' [-Wunused-const-variable] static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; Fix it by adding missing description about this pins Fixes: 775214d3 ("pinctrl: meson: add pinctrl driver support for Meson-S4 Soc") Reported-by:kernel test robot <lkp@intel.com> Signed-off-by:
Qianggui Song <qianggui.song@amlogic.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220330023720.18238-1-qianggui.song@amlogic.comSigned-off-by:
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Fabien Parent authored
Set the pinctrl driver as built-in by default if ARM64 and ARCH_MEDIATEK are enabled. Fixes: 6cf5e9ef ("pinctrl: add pinctrl driver on mt8195") Signed-off-by:
Fabien Parent <fparent@baylibre.com> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
Miles Chen <miles.chen@mediatek.com> Link: https://lore.kernel.org/r/20220327160813.2978637-1-fparent@baylibre.comSigned-off-by:
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Caleb Connolly authored
Add support for deferred PIN_CONFIG_INPUT_ENABLE handling. Signed-off-by:
Caleb Connolly <kc@postmarketos.org> Acked-by:
Bartosz Golaszewski <brgl@bgdev.pl> Link: https://lore.kernel.org/r/20220328005005.72492-4-kc@postmarketos.orgSigned-off-by:
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Caleb Connolly authored
Handle the PIN_CONFIG_INPUT_ENABLE param for configuring GPIOs as input. Signed-off-by:
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Caleb Connolly authored
Add support for deferring other params like PIN_CONFIG_INPUT_ENABLE. This will be used to add support for PIN_CONFIG_INPUT_ENABLE to the driver. Fixes: e7165b1d ("pinctrl/rockchip: add a queue for deferred pin output settings on probe") Fixes: 59dd178e ("gpio/rockchip: fetch deferred output settings on probe") Signed-off-by:
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- 21 Apr, 2022 7 commits
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Michael Walle authored
The SoC supports a debug clock output of its internal clocks. Depending on the clk_sel input (GPIO_31) clk_mon (GPIO_30) will output either cpu_clk/64 or sys_clk/64. This is very useful for debugging and is missing in the pinmux table. Add it. Signed-off-by:
Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20220326192848.2944519-2-michael@walle.ccSigned-off-by:
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Michael Walle authored
According to the reference manual, you can mux the PWM output on GPIO27 and GPIO51. This was missing in the pinmux table. Add it. Tested on a LAN9668 on GPIO51. Signed-off-by:
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Michael Walle authored
Convert the ocelot-pinctrl device tree binding to the new YAML format. Additionally to the original binding documentation, add interrupt properties which are optional and already used on several SoCs like SparX-5, Luton, Ocelot and LAN966x but were not documented before. Also, on the sparx5 and the lan966x SoCs there are two items for the reg property. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220319204628.1759635-7-michael@walle.ccSigned-off-by:
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Rohit Agarwal authored
PMX65 pmic support gpio controller so add compatible. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/1649048650-14059-3-git-send-email-quic_rohiagar@quicinc.comSigned-off-by:
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Rohit Agarwal authored
Add support for the PMX65 GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by:
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Stefan Wahren authored
The commit c8013355 ("ARM: dts: gpio-ranges property is now required") fixed the GPIO probing issues caused by "pinctrl: bcm2835: Change init order for gpio hogs". This changed only the kernel DTS files. Unfortunately it isn't guaranteed that these files are shipped to all users. So implement the necessary backward compatibility for BCM2835 and BCM2711 platform. Fixes: 266423e6 ("pinctrl: bcm2835: Change init order for gpio hogs") Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Tested-by:
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Stefan Wahren authored
Since commit 2ab73c6d ("gpio: Support GPIO controllers without pin-ranges") the device tree nodes of GPIO controller need the gpio-ranges property to handle gpio-hogs. Unfortunately it's impossible to guarantee that every new kernel is shipped with an updated device tree binary. In order to provide backward compatibility with those older DTB, we need a callback within of_gpiochip_add_pin_range() so the relevant platform driver can handle this case. Fixes: 2ab73c6d ("gpio: Support GPIO controllers without pin-ranges") Signed-off-by:
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- 19 Apr, 2022 4 commits
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Nícolas F. R. A. Prado authored
Add the gpio-line-names optional property to the pinctrl-mt8192 binding to prevent dt_binding_check warnings when it is present in the pinctrl node in the Devicetree. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Acked-by:
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Nícolas F. R. A. Prado authored
Add the mediatek,pull-up-adv property to the pinctrl-mt8192 dt-binding to allow configuring pull-up resistors on the pins of MT8192. It is the same as in mt8183-pinctrl. Signed-off-by:
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Nícolas F. R. A. Prado authored
Add the mediatek,drive-strength-adv property to the pinctrl-mt8192 dt-binding to allow further drive current adjustments for I2C nodes on MT8192. It is the same as in mt8183-pinctrl. Signed-off-by:
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Nícolas F. R. A. Prado authored
On mt8192, the pinctrl node has pinctrl groups to group pin configurations. Each pinctrl group contains one or more pinmux subnodes to list needed pins and their configurations. By supporting multiple subnodes, we can configure different pin characteristics (driving/pull-up/pull-down/etc.) in a pinctrl group. Update the mt8192 pinctrl dt-binding to add the missing pinctrl group node that wraps the pinmux subnodes and update the example at the end. While at it, also remove the example embedded in the description since it is redundant to the already supplied example at the end. This same change was done for mt8195 in commit 79dcd4e8 ("dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations"). Signed-off-by:
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- 17 Apr, 2022 8 commits
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Jae Hyun Yoo authored
Add FWQSPI function/group to support QSPI mode on the dedicated FWSPI interface. Signed-off-by:
Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by:
Andrew Jeffery <andrew@aj.id.au> Acked-by:
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Johnny Huang authored
Add FWSPIDQ2 (AE12) and FWSPIDQ3 (AF12) function-group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0# (AB14), FWSPICK (AF13), FWSPIMOSI (AC14) and FWSPIMISO (AB13). Signed-off-by:
Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by:
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Jae Hyun Yoo authored
FWQSPID is not a group of FWSPID so remove it. Fixes: 7488838f ("dt-bindings: pinctrl: aspeed: Document AST2600 pinmux") Signed-off-by:
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Jae Hyun Yoo authored
FWSPIDQ2 and FWSPIDQ3 are not part of FWSPI18 interface so remove FWQSPID group in pinctrl. These pins must be used with the FWSPI pins that are dedicated for boot SPI interface which provides same 3.3v logic level. Fixes: 2eda1cde ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by:
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Chris Packham authored
This pinctrl driver supports the 98DX25xx and 98DX35xx family of chips from Marvell. It is based on the Marvell SDK with additions for various (non-gpio) pin configurations based on the datasheet. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220414233055.586962-3-chris.packham@alliedtelesis.co.nzSigned-off-by:
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Chris Packham authored
Add JSON schema for marvell,ac5-pinctrl present on the Marvell 98DX2530 SoC. Signed-off-by:
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Bhupesh Sharma authored
Specify the PDC mapping for SM8150, so that gpio interrupts are properly mapped to the wakeup IRQs of the PDC. Cc: Maulik Shah <quic_mkshah@quicinc.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20220226184028.111566-3-bhupesh.sharma@linaro.orgSigned-off-by:
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Bhupesh Sharma authored
Add the compatible string for SM8150 SoC from Qualcomm. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Marc Zyngier <maz@kernel.org> Acked-by:
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- 03 Apr, 2022 3 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-traceLinus Torvalds authored
Pull more tracing updates from Steven Rostedt: - Rename the staging files to give them some meaning. Just stage1,stag2,etc, does not show what they are for - Check for NULL from allocation in bootconfig - Hold event mutex for dyn_event call in user events - Mark user events to broken (to work on the API) - Remove eBPF updates from user events - Remove user events from uapi header to keep it from being installed. - Move ftrace_graph_is_dead() into inline as it is called from hot paths and also convert it into a static branch. * tag 'trace-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace: tracing: Move user_events.h temporarily out of include/uapi ftrace: Make ftrace_graph_is_dead() a static branch tracing: Set user_events to BROKEN tracing/user_events: Remove eBPF interfaces tracing/user_events: Hold event_mutex during dyn_event_add proc: bootconfig: Add null pointer check tracing: Rename the staging files for trace_events
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds authored
Pull clk fix from Stephen Boyd: "A single revert to fix a boot regression seen when clk_put() started dropping rate range requests. It's best to keep various systems booting so we'll kick this out and try again next time" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: Revert "clk: Drop the rate range on clk_put()"
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