1. 08 Jan, 2017 2 commits
    • Grygorii Strashko's avatar
      net: ethernet: ti: cpdma: fix desc re-queuing · 12a303e3
      Grygorii Strashko authored
      The currently processing cpdma descriptor with EOQ flag set may
      contain two values in Next Descriptor Pointer field:
      - valid pointer: means CPDMA missed addition of new desc in queue;
      - null: no more descriptors in queue.
      In the later case, it's not required to write to HDP register, but now
      CPDMA does it.
      
      Hence, add additional check for Next Descriptor Pointer != null in
      cpdma_chan_process() function before writing in HDP register.
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      12a303e3
    • Grygorii Strashko's avatar
      net: ethernet: ti: cpdma: am437x: allow descs to be plased in ddr · a6c83ccf
      Grygorii Strashko authored
      It's observed that cpsw/cpdma is not working properly when CPPI
      descriptors are placed in DDR instead of internal CPPI RAM on am437x
      SoC:
      - rx/tx silently stops processing packets;
      - or - after boot it's working for sometime, but stuck once Network
      load is increased (ping is working, but iperf is not).
      (The same issue has not been reproduced on am335x and am57xx).
      
      It seems that write to HDP register processed faster by interconnect
      than writing of descriptor memory buffer in DDR, which is probably
      caused by store buffer / write buffer differences as these functions
      are implemented differently across devices. So, to fix this i come up
      with two minimal, required changes:
      
      1) all accesses to the channel register HDP/CP/RXFREE registers should
      be done using sync IO accessors readl()/writel(), because all previous
      memory writes writes have to be completed before starting channel
      (write to HDP) or completing desc processing.
      
      2) the change 1 only doesn't work on am437x and additional reading of
      desc's field is required right after the new descriptor was filled
      with data and before pointer on it will be stored in
      prev_desc->hw_next field or HDP register.
      
      In addition, to above changes this patch eliminates all relaxed ordering
      I/O accessors in this driver as suggested by David Miller to avoid such
      kind of issues in the future, but with one exception - relaxed IO accessors
      will still be used to fill desc in cpdma_chan_submit(), which is safe as
      there is read barrier at the end of write sequence, and because sync IO
      accessors usage here will affect on net performance.
      Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a6c83ccf
  2. 07 Jan, 2017 9 commits
  3. 06 Jan, 2017 23 commits
  4. 05 Jan, 2017 6 commits