- 23 Apr, 2024 19 commits
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Maíra Canal authored
Create a function to decouple the stats calculation from the printing. This will be useful in the next step when we add a seqcount to protect the stats. Signed-off-by:
Maíra Canal <mcanal@igalia.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240420213632.339941-6-mcanal@igalia.com
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Maíra Canal authored
Given a set of GPU stats, that is, a `struct v3d_stats` related to a queue in a given context, create a function that can update this set of GPU stats. Signed-off-by:
Jose Maria Casanova Crespo <jmcasanova@igalia.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240420213632.339941-5-mcanal@igalia.com
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Maíra Canal authored
This will make it easier to instantiate the GPU stats variables and it will create a structure where we can store all the variables that refer to GPU stats. Note that, when we created the struct `v3d_stats`, we renamed `jobs_sent` to `jobs_completed`. This better express the semantics of the variable, as we are only accounting jobs that have been completed. Signed-off-by:
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Maíra Canal authored
Currently, we manually perform all operations to update the GPU stats variables. Apart from the code repetition, this is very prone to errors, as we can see on commit 35f4f8c9 ("drm/v3d: Don't increment `enabled_ns` twice"). Therefore, create two functions to manage updating all GPU stats variables. Now, the jobs only need to call for `v3d_job_update_stats()` when the job is done and `v3d_job_start_stats()` when starting the job. Co-developed-by:
Tvrtko Ursulin <tursulin@igalia.com> Signed-off-by:
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Xuxin Xiong authored
Add support for the following panel: CSOT MNB601LS1-1 Signed-off-by:
Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
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Tony Lindgren authored
The hs_rate and lp_rate may be used by the dsi host for timing calculations. The tc358775 has a maximum bit rate of 1 Gbps/lane, tc358765 has maximurate of 800 Mbps per lane. Reviewed-by:
Michael Walle <mwalle@kernel.org> Signed-off-by:
Tony Lindgren <tony@atomide.com> Reviewed-by:
Robert Foss <rfoss@kernel.org> Signed-off-by:
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Tony Lindgren authored
The tc358775 bridge is pin compatible with earlier tc358765 according to the tc358774xbg_datasheet_en_20190118.pdf documentation. Compared to the tc358765, the tc358775 supports a STBY GPIO and higher data rates. The tc358765 has a register bit for video event mode vs video pulse mode. We must set it to video event mode for the LCD output to work, and on the tc358775, this bit no longer exists. Looks like the registers seem to match otherwise based on a quick glance comparing the defines to the earlier Android kernel tc358765 driver. Reviewed-by:
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Tony Lindgren authored
Set pre_enable_prev_first to ensure the previous bridge is enabled first. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
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Tony Lindgren authored
Burst and low-power modes are supported both for tc358765 and tc358775. Reviewed-by:
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Tony Lindgren authored
The current code assumes the data-lanes property is configured on the DSI host side instead of the bridge side, and assumes DSI host endpoint 1. Let's standardize on what the other bridge drivers are doing and parse the data-lanes property for the bridge. Only if data-lanes property is not found, let's be nice and also check the DSI host for old dtb in use and warn. And as Dmitry pointed out, the lanes for the host and the bridge may be different because the lanes may be swapped on the host side. Reviewed-by:
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Michael Walle authored
The stby pin is optional. It is only needed for power-up and down sequencing. It is not needed, if the power rails cannot by dynamically enabled. Because the GPIO is now optional, remove the error message. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Michael Walle authored
The bridge always uses 24bpp internally. Therefore, for jeida-18 mapping we need to discard the lowest two bits for each channel and thus starting with LV_[RGB]2. jeida-24 has the same mapping but uses four lanes instead of three, with the forth pair transmitting the lowest two bits of each channel. Thus, the mapping between jeida-18 and jeida-24 is actually the same, except that one channel is turned off (by selecting the RGB666 format in VPCTRL). While at it, remove the bogus comment about the hardware default because the default is overwritten in any case. Tested with a jeida-18 display (Evervision VGG644804). Fixes: b2697559 ("display/drm/bridge: TC358775 DSI/LVDS driver") Signed-off-by:
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Tony Lindgren authored
The tc358765 is similar to tc358775. The tc358765 just an earlier version of the hardware, and it's pin and register compatible with tc358775 for most part. From the binding point of view the only difference is that the tc358765 does not have stdby-gpios. Reviewed-by:
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Tony Lindgren authored
The device uses a clock lane, and 1 to 4 DSI data lanes. Let's add the data-lanes property starting at 1 similar to what the other bridge bindings are doing. Let's also drop the data-lanes properties in the example for the DSI host controller to avoid confusion. The configuration of the DSI host depends on the controller used and is unrelated to the bridge binding. Reviewed-by:
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Michael Walle authored
For a normal operation, the stby GPIO is not needed. The reset pin is required because once the PPI (PHY protocol interface) is started, it can only be stopped by asserting the reset pin. Signed-off-by:
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Dharma Balasubiramani authored
Add the newly added LVDS controller for the SAM9X7 SoC to the existing MAINTAINERS entry. Signed-off-by:
Dharma Balasubiramani <dharma.b@microchip.com> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20240421011050.43265-4-dharma.b@microchip.comSigned-off-by:
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Dharma Balasubiramani authored
Add a new LVDS controller driver for sam9x7 which does the following: - Prepares and enables the LVDS Peripheral clock - Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself to the global bridge list. - Identifies its output endpoint as panel and adds it to the encoder display pipeline - Enables the LVDS serializer Signed-off-by:
Manikandan Muralidharan <manikandan.m@microchip.com> Signed-off-by:
Hari Prasath Gujulan Elango <hari.prasathge@microchip.com> Reviewed-by:
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Dharma Balasubiramani authored
Add the 'sam9x75-lvds' compatible binding, which describes the Low Voltage Differential Signaling (LVDS) Controller found on some Microchip's sam9x7 series System-on-Chip (SoC) devices. This binding will be used to define the properties and configuration for the LVDS Controller in DT. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240421011050.43265-2-dharma.b@microchip.comSigned-off-by:
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Maxime Ripard authored
Maíra needs a backmerge to apply v3d patches, and Danilo for some nouveau patches. Signed-off-by:Maxime Ripard <mripard@kernel.org>
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- 22 Apr, 2024 21 commits
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Acked-by:
Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/56ee6b7c3c018df55f5fe48a3e6d705dbad5ef74.1713273659.git.jani.nikula@intel.comSigned-off-by:
Jani Nikula <jani.nikula@intel.com>
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Acked-by:
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Acked-by:
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Reviewed-by:
Noralf Trønnes <noralf@tronnes.org> Link: https://patchwork.freedesktop.org/patch/msgid/c519a9b9d3c3c9a413de33b99b97a1120f774f2d.1713273659.git.jani.nikula@intel.comSigned-off-by:
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Acked-by:
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Acked-by:
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Reviewed-by:
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Reviewed-by:
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Jani Nikula authored
Prefer struct drm_edid based functions over struct edid. Reviewed-by:
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Arunpravin Paneer Selvam authored
Add a new test case for the drm buddy clear and dirty allocation. v2:(Matthew) - make size as u32 - rename PAGE_SIZE with SZ_4K - dont fragment the address space for all the order allocation iterations. we can do it once and just increment and allocate the size. - create new mm with non power-of-two size to ensure the multi-root force_merge during fini. v3: - add randomness in size calculation(Matthew) Signed-off-by:Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Suggested-by:
Christian König <christian.koenig@amd.com>
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Arunpravin Paneer Selvam authored
Add clear page support in vram memory region. v1(Christian): - Dont handle clear page as TTM flag since when moving the BO back in from GTT again we don't need that. - Make a specialized version of amdgpu_fill_buffer() which only clears the VRAM areas which are not already cleared - Drop the TTM_PL_FLAG_WIPE_ON_RELEASE check in amdgpu_object.c v2: - Modify the function name amdgpu_ttm_* (Alex) - Drop the delayed parameter (Christian) - handle amdgpu_res_cleared(&cursor) just above the size calculation (Christian) - Use AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE for clearing the buffers in the free path to properly wait for fences etc.. (Christian) v3(Christian): - Remove buffer clear code in VRAM manager instead change the AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE handling to set the DRM_BUDDY_CLEARED flag. - Remove ! from amdgpu_res_cleared(&cursor) check. v4(Christian): - vres flag setting move to vram manager file - use dma_fence_get_stub in amdgpu_ttm_clear_buffer function - make fence a mandatory parameter and drop the if and the get/put dance Signed-off-by:Felix Kuehling <felix.kuehling@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240419063538.11957-2-Arunpravin.PaneerSelvam@amd.comSigned-off-by:
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Arunpravin Paneer Selvam authored
- Add tracking clear page feature. - Driver should enable the DRM_BUDDY_CLEARED flag if it successfully clears the blocks in the free path. On the otherhand, DRM buddy marks each block as cleared. - Track the available cleared pages size - If driver requests cleared memory we prefer cleared memory but fallback to uncleared if we can't find the cleared blocks. when driver requests uncleared memory we try to use uncleared but fallback to cleared memory if necessary. - When a block gets freed we clear it and mark the freed block as cleared, when there are buddies which are cleared as well we can merge them. Otherwise, we prefer to keep the blocks as separated. - Add a function to support defragmentation. v1: - Depends on the flag check DRM_BUDDY_CLEARED, enable the block as cleared. Else, reset the clear flag for each block in the list(Christian) - For merging the 2 cleared blocks compare as below, drm_buddy_is_clear(block) != drm_buddy_is_clear(buddy)(Christian) - Defragment the memory beginning from min_order till the required memory space is available. v2: (Matthew) - Add a wrapper drm_buddy_free_list_internal for the freeing of blocks operation within drm buddy. - Write a macro block_incompatible() to allocate the required blocks. - Update the xe driver for the drm_buddy_free_list change in arguments. - add a warning if the two blocks are incompatible on defragmentation - call full defragmentation in the fini() function - place a condition to test if min_order is equal to 0 - replace the list with safe_reverse() variant as we might remove the block from the list. v3: - fix Gitlab user reported lockup issue. - Keep DRM_BUDDY_HEADER_CLEAR define sorted(Matthew) - modify to pass the root order instead max_order in fini() function(Matthew) - change bool 1 to true(Matthew) - add check if min_block_size is power of 2(Matthew) - modify the min_block_size datatype to u64(Matthew) v4: - rename the function drm_buddy_defrag with __force_merge. - Include __force_merge directly in drm buddy file and remove the defrag use in amdgpu driver. - Remove list_empty() check(Matthew) - Remove unnecessary space, headers and placement of new variables(Matthew) - Add a unit test case(Matthew) v5: - remove force merge support to actual range allocation and not to bail out when contains && split(Matthew) - add range support to force merge function. v6: - modify the alloc_range() function clear page non merged blocks allocation(Matthew) - correct the list_insert function name(Matthew). Signed-off-by: -
Neil Armstrong authored
Disable the px_clk when setting the rate to recover a fully configured and correctly reset VCLK clock tree after the rate is set. Fixes: 77d9e1e6 ("drm/meson: add support for MIPI-DSI transceiver") Reviewed-by:
Nicolas Belin <nbelin@baylibre.com> Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-4-99ecdfdc87fc@linaro.orgSigned-off-by:
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Ville Syrjälä authored
Fix the typos in the plane SIZE_HINTS kernel docs. Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Fixes: 9677547d ("drm: Introduce plane SIZE_HINTS property") Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240418114218.9162-1-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
DisplayID spec v1.3 revision history notes do claim that the toplogy block was added in v1.3 so requiring structure v1.2 would seem correct, but there is at least one EDID in edid.tv with a topology block and structure v1.0. And there are also EDIDs with DisplayID structure v1.3 which seems to be totally incorrect as DisplayID spec v1.3 lists structure v1.2 as the only legal value. Unfortunately I couldn't find copies of DisplayID spec v1.0-v1.2 anywhere (even on vesa.org), so I'll have to go on empirical evidence alone. We used to parse the topology block on all v1.x structures until the check for structure v2.0 was added. Let's go back to doing that as the evidence does suggest that there are DisplayIDs in the wild that would miss out on the topology stuff otherwise. Also toss out DISPLAY_ID_STRUCTURE_VER_12 entirely as it doesn't appear we can really use it for anything. I *think* we could technically skip all the structure version checks as the block tags shouldn't conflict between v2.0 and v1.x. But no harm in having a bit of extra sanity checks I guess. So far I'm not aware of any user reported regressions from overly strict check, but I do know that it broke igt/kms_tiled_display's fake DisplayID as that one gets generated with structure v1.0. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com> Fixes: c5a486af ("drm/edid: parse Tiled Display Topology Data Block for DisplayID 2.0") Signed-off-by:
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David Wronek authored
Add support for the 2560x1600@90Hz OLED panel by EDO bundled with a Raydium RM69380 controller, as found on the Lenovo Xiaoxin Pad Pro 2021. Reviewed-by:
David Wronek <david@mainlining.org> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Acked-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Link: https://lore.kernel.org/r/20240417-raydium-rm69380-driver-v4-2-e9c2337d0049@mainlining.orgSigned-off-by:
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David Wronek authored
Raydium RM69380 is a display driver IC used to drive OLED DSI panels. Add a dt-binding for it. Signed-off-by:
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Jacobe Zang authored
This add Khadas TS050 V2 Panel and make it compatible with old one. Controller of V2 panel is "Himax HX8399-C" and the old panel is "NT35596". In driver file, the only different between them is the timing squence. Signed-off-by:
Jacobe Zang <jacobe.zang@wesion.com> Reviewed-by:
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Jacobe Zang authored
This add the bindings for the Khadas TS050 V2 1080x1920 5" LCD DSI panel designed to work with the Khadas VIM3 and VIM3L Single Board Computers. Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240419014852.715125-2-jacobe.zang@wesion.comSigned-off-by:
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Dan Carpenter authored
These variables should be u32 instead of u64 because they're only storing u32 values. Also static checkers complain when we do: suspended_slots &= ~upd_ctx.timedout_mask; In this code "suspended_slots" is a u64 and "upd_ctx.timedout_mask". The mask clears out the top 32 bits which would likely be a bug if anything were stored there. Signed-off-by:
Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by:
Steven Price <steven.price@arm.com> Reviewed-by:
Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by:
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Dave Airlie authored
Linux 6.9-rc5 I've had a persistent msm failure on clang, and the fix is in fixes so just pull it back to fix that. Signed-off-by:Dave Airlie <airlied@redhat.com>
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