- 07 Jul, 2021 1 commit
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Marek Vasut authored
Since 00b80ac9 ("spi: imx: mx51-ecspi: Move some initialisation to prepare_message hook."), the MX51_ECSPI_CONFIG write no longer happens in prepare_transfer hook, but rather in prepare_message hook, however the MX51_ECSPI_CONFIG delay is still left in prepare_transfer hook and thus has no effect. This leads to low bus frequency operation problems described in 6fd8b850 ("spi: spi-imx: Fix out-of-order CS/SCLK operation at low speeds") again. Move the MX51_ECSPI_CONFIG write delay into the prepare_message hook as well, thus reinstating the low bus frequency fix. Fixes: 00b80ac9 ("spi: imx: mx51-ecspi: Move some initialisation to prepare_message hook.") Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20210703022300.296114-1-marex@denx.deSigned-off-by:
Mark Brown <broonie@kernel.org>
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- 30 Jun, 2021 1 commit
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Alain Volmat authored
In case of Full-Duplex mode, DXP flag is set when RXP and TXP flags are set. But to avoid 2 different handlings, just add TXP and RXP flag in the mask instead of DXP, and then keep the initial handling of TXP and RXP events. Also rephrase comment about EOTIE which is one of the interrupt enable bits. It is not triggered by any event. Signed-off-by:
Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by:
Alain Volmat <alain.volmat@foss.st.com> Reviewed-by:
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- 25 Jun, 2021 2 commits
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Vinod Koul authored
Some controllers like qcom geni need the parent device to be used for dma mapping, so add a dma_map_dev field and let drivers fill this to be used as mapping device Signed-off-by:
Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210625052213.32260-4-vkoul@kernel.orgSigned-off-by:
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Nobuhiro Iwamatsu authored
Convert spi for Xilinx Zynq UltraScale+ MPSoC GQSPI bindings documentation to YAML. Signed-off-by:
Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210613214317.296667-1-iwamatsu@nigauri.orgSigned-off-by:
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- 24 Jun, 2021 1 commit
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Colin Ian King authored
There is an assignment of ancillary->mode to itself which looks dubious since the proceeding comment states that the speed and mode is taken over from the SPI main device, indicating that ancillary->mode should assigned using the value spi->mode. Fix this. Addresses-Coverity: ("Self assignment") Fixes: 0c79378c ("spi: add ancillary device support") Signed-off-by:Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210623172300.161484-1-colin.king@canonical.comSigned-off-by:
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- 23 Jun, 2021 9 commits
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Mark Brown authored
Changes in v10: - The internal CS inactive function is only supported after VER 0x00110002 Changes in v9: - Conver to use CS GPIO description Changes in v8: - There is a problem with the version 7 mail format. resend it Changes in v7: - Fall back "rockchip,rv1126-spi" to "rockchip,rk3066-spi" Changes in v6: - Consider to compatibility, the "rockchip,rk3568-spi" is removed in Series-changes v5, so the commit massage should also remove the corresponding information Changes in v5: - Change to leave one compatible id rv1126, and rk3568 is compatible with rv1126 Changes in v4: - Adjust the order patches - Simply commit massage like redundancy "application" content Changes in v3: - Fix compile error which is find by Sascha in [v2,2/8] Jon Lin (6): dt-bindings: spi: spi-rockchip: add description for rv1126 spi: rockchip: add compatible string for rv1126 spi: rockchip: Set rx_fifo interrupt waterline base on transfer item spi: rockchip: Wait for STB status in slave mode tx_xfer spi: rockchip: Support cs-gpio spi: rockchip: Support SPI_CS_HIGH .../devicetree/bindings/spi/spi-rockchip.yaml | 1 + drivers/spi/spi-rockchip.c | 55 ++++++++++++++----- 2 files changed, 41 insertions(+), 15 deletions(-) -- 2.17.1
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Wolfram Sang authored
dmaengine_terminate_all() is deprecated in favor of explicitly saying if it should be sync or async. Here, we want dmaengine_terminate_sync() because there is no other synchronization code in the driver to handle an async case. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210623095843.3228-3-wsa+renesas@sang-engineering.comSigned-off-by:
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Wolfram Sang authored
dmaengine_terminate_all() is deprecated in favor of explicitly saying if it should be sync or async. Here, we want dmaengine_terminate_sync() because there is no other synchronization code in the driver to handle an async case. Signed-off-by:
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Jon Lin authored
The description below will be used for rv1126.dtsi or compatible one in the future Signed-off-by:
Jon Lin <jon.lin@rock-chips.com> Link: https://lore.kernel.org/r/20210621104800.19088-2-jon.lin@rock-chips.comSigned-off-by:
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Jon Lin authored
1.Add standard spi-cs-high support 2.Refer to spi-controller.yaml for details Signed-off-by:
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Jon Lin authored
1.Add standard cs-gpio support 2.Refer to spi-controller.yaml for details Signed-off-by:
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Jon Lin authored
After ROCKCHIP_SPI_VER2_TYPE2, SR->STB is a more accurate judgment bit for spi slave transmition. Signed-off-by:
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Jon Lin authored
The error here is to calculate the width as 8 bits. In fact, 16 bits should be considered. Signed-off-by:
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Jon Lin authored
Add compatible string for rv1126 for potential applications. Signed-off-by:
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- 22 Jun, 2021 2 commits
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Sebastian Reichel authored
Add binding support for devices, that have more than one chip select. A typical example are SPI connected microcontroller, that can also be programmed over SPI like NXP Kinetis or chips with a configuration and a data chip select, such as Microchip's MRF89XA transceiver. Reviewed-by:
Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20210621175359.126729-3-sebastian.reichel@collabora.comSigned-off-by:
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Sebastian Reichel authored
Introduce support for ancillary devices, similar to existing implementation for I2C. This is useful for devices having multiple chip-selects, for example some microcontrollers provide a normal SPI interface and a flashing SPI interface. Signed-off-by:
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- 17 Jun, 2021 2 commits
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Nobuhiro Iwamatsu authored
Convert SPI for Xilinx bindings documentation to YAML schemas. Signed-off-by:
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Nobuhiro Iwamatsu authored
Convert spi for Cadence SPI bindings documentation to YAML. Signed-off-by:
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- 15 Jun, 2021 2 commits
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Patrice Chotard authored
Remove struct stm32_qspi_flash's field qspi which is not used. Fixes: c530cd1d ("spi: spi-mem: add stm32 qspi controller") Signed-off-by:
Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210615090115.30702-1-patrice.chotard@foss.st.comSigned-off-by:
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Marco Felsch authored
Add OF support as already done for ACPI to take driver MODULE_DEVICE_TABLE(of, ..) into account. For example with this change a spi nor device MODALIAS changes from: MODALIAS=spi:spi-nor to MODALIAS=of:Nspi-flashT(null)Cjedec,spi-nor Signed-off-by:
Marco Felsch <m.felsch@pengutronix.de> Link: https://lore.kernel.org/r/20210525091003.18228-1-m.felsch@pengutronix.deSigned-off-by:
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- 14 Jun, 2021 3 commits
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zpershuai authored
when meson_spicc_clk_init returns failed, it should goto the out_clk label. Signed-off-by:
zpershuai <zpershuai@gmail.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/1623562156-21995-1-git-send-email-zpershuai@gmail.comSigned-off-by:
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zpershuai authored
In meson_spifc_probe function, when enable the device pclk clock is error, it should use clk_disable_unprepare to release the core clock. Signed-off-by:
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Yang Yingliang authored
Fix the following make W=1 warning: drivers/spi/spi-mem.c:819: warning: expecting prototype for spi_mem_driver_unregister_with_owner(). Prototype was for spi_mem_driver_unregister() instead Signed-off-by:
Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20210601120721.3198488-1-yangyingliang@huawei.comSigned-off-by:
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- 09 Jun, 2021 1 commit
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Greg Kroah-Hartman authored
No one seems to be using this global and exported function, so remove it as it is no longer needed. Cc: Mark Brown <broonie@kernel.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://lore.kernel.org/r/20210609071918.2852069-1-gregkh@linuxfoundation.orgSigned-off-by:
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- 07 Jun, 2021 1 commit
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Jay Fang authored
This patch uses debugfs_regset32 interface to create the registers dump file. Use it instead of creating a generic debugfs file with manually written read callback function. With these entries, users can check all the SPI controller registers during run time. Signed-off-by:
Jay Fang <f.fangjian@huawei.com> Link: https://lore.kernel.org/r/1622789718-13977-1-git-send-email-f.fangjian@huawei.comSigned-off-by:
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- 04 Jun, 2021 1 commit
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Patrice Chotard authored
Fix the following compilation warning using W=1 build: arm-linux-gnueabi-ld: drivers/spi/spi-stm32-qspi.o: in function `stm32_qspi_poll_status': Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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- 03 Jun, 2021 6 commits
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Mark Brown authored
Patrice Chotard <patrice.chotard@foss.st.com>: From: Patrice Chotard <patrice.chotard@foss.st.com> This series adds support for the spi_mem_poll_status() spinand interface. Some QSPI controllers allows to poll automatically memory status during operations (erase, read or write). This allows to offload the CPU for this task. STM32 QSPI is supporting this feature, driver update are also part of this series. Changes in v5: - Update spi_mem_read_status() description. - Update poll_status() description API by indicating that data buffer is filled with last status value. - Update timeout parameter by timeout_ms in spi_mem_poll_status() prototype. - Remove parenthesys arount -EINVAL in spi_mem_poll_status(). - Add missing spi_mem_supports_op() call in stm32_qspi_poll_status(). - Add Boris Reviewed-by for patch 1 and 2. Changes in v4: - Remove init_completion() from spi_mem_probe() added in v2. - Add missing static for spi_mem_read_status(). - Check if operation in spi_mem_poll_status() is a READ. - Update patch 2 commit message. - Add comment which explains how delays has been calculated. - Rename SPINAND_STATUS_TIMEOUT_MS to SPINAND_WAITRDY_TIMEOUT_MS. Chnages in v3: - Add spi_mem_read_status() which allows to read 8 or 16 bits status. - Add initial_delay_us and polling_delay_us parameters to spi_mem_poll_status(). and also to poll_status() callback. - Move spi_mem_supports_op() in SW-based polling case. - Add delay before invoquing read_poll_timeout(). - Remove the reinit/wait_for_completion() added in v2. - Add initial_delay_us and polling_delay_us parameters to spinand_wait(). - Add SPINAND_READ/WRITE/ERASE/RESET_INITIAL_DELAY_US and SPINAND_READ/WRITE/ERASE/RESET_POLL_DELAY_US defines. - Remove spi_mem_finalize_op() API added in v2. Changes in v2: - Indicates the spi_mem_poll_status() timeout unit - Use 2-byte wide status register - Add spi_mem_supports_op() call in spi_mem_poll_status() - Add completion management in spi_mem_poll_status() - Add offload/non-offload case management in spi_mem_poll_status() - Optimize the non-offload case by using read_poll_timeout() - mask and match stm32_qspi_poll_status()'s parameters are 2-byte wide - Make usage of new spi_mem_finalize_op() API in stm32_qspi_wait_poll_status() Patrice Chotard (3): spi: spi-mem: add automatic poll status functions mtd: spinand: use the spi-mem poll status APIs spi: stm32-qspi: add automatic poll status feature drivers/mtd/nand/spi/core.c | 45 +++++++++++++------ drivers/spi/spi-mem.c | 86 ++++++++++++++++++++++++++++++++++++ drivers/spi/spi-stm32-qspi.c | 86 ++++++++++++++++++++++++++++++++---- include/linux/mtd/spinand.h | 22 +++++++++ include/linux/spi/spi-mem.h | 16 +++++++ 5 files changed, 234 insertions(+), 21 deletions(-) base-commit: 6efb943b -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -
Dan Sneddon authored
The current implementation of the driver holds a spin lock for the duration of the transfer, releasing it only to enable interrupts for short periods of time. As this would prevent any interrupt from happening, this could cause system performance issues every time a SPI message is sent. Since the spi core now handles message syncronization we can reduce the amount of time the spin-lock is held to the regions where both the calling thread and the interrupt might interract. Signed-off-by:
Dan Sneddon <dan.sneddon@microchip.com> Link: https://lore.kernel.org/r/20210602160816.4890-2-dan.sneddon@microchip.comSigned-off-by:
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Dan Sneddon authored
Switch from using our own transfer_one_message routine to using the one provided by the SPI core. Signed-off-by:
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Patrice Chotard authored
STM32 QSPI is able to automatically poll a specified register inside the memory and relieve the CPU from this task. As example, when erasing a large memory area, we got cpu load equal to 50%. This patch allows to perform the same operation with a cpu load around 2%. Signed-off-by:
Christophe Kerello <christophe.kerello@foss.st.com> Signed-off-by:
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Patrice Chotard authored
Make use of spi-mem poll status APIs to let advanced controllers optimize wait operations. This should also fix the high CPU usage for system that don't have a dedicated STATUS poll block logic. Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com> Acked-by:
Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20210518162754.15940-3-patrice.chotard@foss.st.comSigned-off-by:
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Patrice Chotard authored
With STM32 QSPI, it is possible to poll the status register of the device. This could be done to offload the CPU during an operation (erase or program a SPI NAND for example). spi_mem_poll_status API has been added to handle this feature. This new function take care of the offload/non-offload cases. For the non-offload case, use read_poll_timeout() to poll the status in order to release CPU during this phase. For example, previously, when erasing large area, in non-offload case, CPU load can reach ~50%, now it decrease to ~35%. Signed-off-by:
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- 02 Jun, 2021 1 commit
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Lukas Wunner authored
Since commit 571e31fa ("spi: bcm2835: Cache CS register value for ->prepare_message()"), the number of slaves has been limited by a compile-time constant. This was necessitated by statically-sized arrays in the driver private data which contain per-slave register values. As suggested by Mark, move those register values to a per-slave controller_state which is allocated on ->setup and freed on ->cleanup. The limitation on the number of slaves is thus lifted. Signed-off-by:
Lukas Wunner <lukas@wunner.de> Cc: Joe Burmeister <joe.burmeister@devtank.co.uk> Cc: Phil Elwell <phil@raspberrypi.com> Link: https://lore.kernel.org/r/a847c01f09400801e74e0630bf5a0197591554da.1622150204.git.lukas@wunner.deSigned-off-by:
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- 01 Jun, 2021 2 commits
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Mark Brown authored
Merge branch 'for-5.13' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-5.14
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Lukas Wunner authored
Commit c7299fea ("spi: Fix spi device unregister flow") changed the SPI core's behavior if the ->setup() hook returns an error upon adding an spi_device: Before, the ->cleanup() hook was invoked to free any allocations that were made by ->setup(). With the commit, that's no longer the case, so the ->setup() hook is expected to free the allocations itself. I've identified 5 drivers which depend on the old behavior and am fixing them up hereinafter: spi-bitbang.c spi-fsl-spi.c spi-omap-uwire.c spi-omap2-mcspi.c spi-pxa2xx.c Importantly, ->setup() is not only invoked on spi_device *addition*: It may subsequently be called to *change* SPI parameters. If changing these SPI parameters fails, freeing memory allocations would be wrong. That should only be done if the spi_device is finally destroyed. I am therefore using a bool "initial_setup" in 4 of the affected drivers to differentiate between the invocation on *adding* the spi_device and any subsequent invocations: spi-bitbang.c spi-fsl-spi.c spi-omap-uwire.c spi-omap2-mcspi.c In spi-pxa2xx.c, it seems the ->setup() hook can only fail on spi_device addition, not any subsequent calls. It therefore doesn't need the bool. It's worth noting that 5 other drivers already perform a cleanup if the ->setup() hook fails. Before c7299fea, they caused a double-free if ->setup() failed on spi_device addition. Since the commit, they're fine. These drivers are: spi-mpc512x-psc.c spi-pl022.c spi-s3c64xx.c spi-st-ssc4.c spi-tegra114.c (spi-pxa2xx.c also already performs a cleanup, but only in one of several error paths.) Fixes: c7299fea ("spi: Fix spi device unregister flow") Signed-off-by:
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- 26 May, 2021 1 commit
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Andy Shevchenko authored
It is helpful to see what state of CS signal was during one or another SPI operation. All the same for SPI setup. Enable tracing of the SPI setup and CS selection. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Message-Id: <20210526195655.75691-1-andriy.shevchenko@linux.intel.com> Signed-off-by:
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- 24 May, 2021 3 commits
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David Bauer authored
All chipsets from AR7100 up to QCA9563 have three dedicated chipselect lines for the integrated SPI controller. Set the number of chipselect lines available on the controller to this value. Signed-off-by:
David Bauer <mail@david-bauer.net> Link: https://lore.kernel.org/r/20210522074453.39299-2-mail@david-bauer.netSigned-off-by:
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David Bauer authored
The ath79 platform has been converted to pure OF. The platform data is not needed anymore because of this. Signed-off-by:
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Lukas Wunner authored
Commit 571e31fa ("spi: bcm2835: Cache CS register value for ->prepare_message()") limited the number of slaves to 3 at compile-time. The limitation was necessitated by a statically-sized array prepare_cs[] in the driver private data which contains a per-slave register value. The commit sought to enforce the limitation at run-time by setting the controller's num_chipselect to 3: Slaves with a higher chipselect are rejected by spi_add_device(). However the commit neglected that num_chipselect only limits the number of *native* chipselects. If GPIO chipselects are specified in the device tree for more than 3 slaves, num_chipselect is silently raised by of_spi_get_gpio_numbers() and the result are out-of-bounds accesses to the statically-sized array prepare_cs[]. As a bandaid fix which is backportable to stable, raise the number of allowed slaves to 24 (which "ought to be enough for anybody"), enforce the limitation on slave ->setup and revert num_chipselect to 3 (which is the number of native chipselects supported by the controller). An upcoming for-next commit will allow an arbitrary number of slaves. Fixes: 571e31fa ("spi: bcm2835: Cache CS register value for ->prepare_message()") Reported-by:
Joe Burmeister <joe.burmeister@devtank.co.uk> Signed-off-by:
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- 21 May, 2021 1 commit
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Jiapeng Chong authored
Eliminate the follow smatch warning: drivers/spi/spi-pxa2xx-pci.c:260 pxa2xx_spi_pci_probe() warn: inconsistent indenting. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/1621590465-73594-1-git-send-email-jiapeng.chong@linux.alibaba.comSigned-off-by:
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