- 09 Jan, 2022 16 commits
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Jisheng Zhang authored
There are no users outside head.S so make secondary_start_common() static. Signed-off-by:
Jisheng Zhang <jszhang@kernel.org> Signed-off-by:
Palmer Dabbelt <palmer@rivosinc.com>
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Jisheng Zhang authored
Except arch_cpu_idle_dead(), no users of this function. So remove cpu_stop() and fold its code into arch_cpu_idle_dead(). Signed-off-by:
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Nick Kossifidis authored
When allocating crash kernel region without explicitly specifying its base address/size, memblock_phys_alloc_range will attempt to allocate memory top to bottom (memblock.bottom_up is false), so the crash kernel region will end up in highmem on 64bit systems. This way swiotlb can't work on the crash kernel, since there won't be any 32bit addressible memory available for the bounce buffers. Try to allocate 32bit addressible memory if available, for the crash kernel by restricting the top search address to be less than SZ_4G. If that fails fallback to the previous behavior. I tested this on HiFive Unmatched where the pci-e controller needs swiotlb to work, with this patch it's possible to access the pci-e controller on crash kernel and mount the rootfs from the nvme. Signed-off-by:
Nick Kossifidis <mick@ics.forth.gr> Fixes: e53d2818 ("RISC-V: Add kdump support") Cc: stable@vger.kernel.org Signed-off-by:
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Nick Kossifidis authored
raw_smp_processor_id() doesn't return the hart id as stated in arch/riscv/include/asm/smp.h, use smp_processor_id() instead to get the cpu id, and cpuid_to_hartid_map() to pass the hart id to the next kernel. This fixes kexec on HiFive Unleashed/Unmatched where cpu ids and hart ids don't match (on qemu-virt they match). Fixes: fba8a867 ("RISC-V: Add kexec support") Signed-off-by:
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Nick Kossifidis authored
On kdump instead of using an intermediate step to relocate the kernel, that lives in a "control buffer" outside the current kernel's mapping, we jump to the crash kernel directly by calling riscv_kexec_norelocate(). The current implementation uses va_pa_offset while switching to physical addressing, however since we moved the kernel outside the linear mapping this won't work anymore since riscv_kexec_norelocate() is part of the kernel mapping and we should use kernel_map.va_kernel_pa_offset, and also take XIP kernel into account. We don't really need to use va_pa_offset on riscv_kexec_norelocate, we can just set STVEC to the physical address of the new kernel instead and let the hart jump to the new kernel on the next instruction after setting SATP to zero. This fixes kdump and is also simpler/cleaner. I tested this on the latest qemu and HiFive Unmatched and works as expected. Fixes: 2bfc6cd8 ("riscv: Move kernel mapping outside of linear mapping") Signed-off-by:
Alexandre Ghiti <alex@ghiti.fr> Cc: stable@vger.kernel.org Signed-off-by:
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Geert Uytterhoeven authored
Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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Geert Uytterhoeven authored
"make dtbs_check": arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected From schema: Documentation/devicetree/bindings/riscv/sifive.yaml arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed: 'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00'] 'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00'] 'sifive,fu540-c000' was expected 'sifive,fu740-c000' was expected 'sifive,fu540' was expected 'sifive,fu740' was expected From schema: Documentation/devicetree/bindings/riscv/sifive.yaml This happens because the "soc" subnode declares compatibility with "sifive,fu540-c000" and "sifive,fu540", while these are only intended for the root node. Fix this by removing the bogus compatible values from the "soc" node. Signed-off-by:Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by:
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Geert Uytterhoeven authored
To improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets. Signed-off-by:
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Geert Uytterhoeven authored
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by:
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Geert Uytterhoeven authored
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Tested-by:
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Geert Uytterhoeven authored
Fix the device node for the clock controller: - Remove bogus "reg-names" property, - Remove unneeded "clock-output-names" property. Signed-off-by:
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Geert Uytterhoeven authored
"make dtbs_check" reports: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Fix this by moving the node out of the "soc" subnode. While at it, rename it to "msspllclk", and drop the now superfluous "clock-output-names" property. Move the actual clock-frequency value to the board DTS, since it is not set until bitstream programming time. Signed-off-by: -
Geert Uytterhoeven authored
Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by:
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Geert Uytterhoeven authored
It does not make sense to have an (empty) chosen node in an SoC-specific .dtsi, as chosen is meant for system-specific configuration. It is already provided in microchip-mpfs-icicle-kit.dts anyway. Fixes: 0fa6107e ("RISC-V: Initial DTS for Microchip ICICLE board") Signed-off-by:
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Geert Uytterhoeven authored
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets. Signed-off-by:
Damien Le Moal <damien.lemoal@opensource.wdc.com> Reviewed-by:
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Geert Uytterhoeven authored
"make dtbs_check": arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$' From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml Fix this by renaming all SPI FLASH nodes to "flash". Signed-off-by:
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- 07 Jan, 2022 3 commits
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Nanyong Sun authored
Add two THP helpers required to create PMD migration swap entries, and enable THP migration via ARCH_ENABLE_THP_MIGRATION. This can reduce time of THP migration without splitting and guarantee the migrated pages are still contiguous. Signed-off-by:
Nanyong Sun <sunnanyong@huawei.com> Signed-off-by:
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Nanyong Sun authored
This is a preparation for enabling THP migration. As the commit b65399f6("arm64/mm: Change THP helpers to comply with generic MM semantics") mentioned, pmd_present() and pmd_trans_huge() are expected to behave in the following manner: ------------------------------------------------------------------------- | PMD states | pmd_present | pmd_trans_huge | ------------------------------------------------------------------------- | Mapped | Yes | Yes | ------------------------------------------------------------------------- | Splitting | Yes | Yes | ------------------------------------------------------------------------- | Migration/Swap | No | No | ------------------------------------------------------------------------- At present the PROT_NONE bit reuses the READ bit could not comply with above semantics with two problems: 1. When splitting a PMD THP, PMD is first invalidated with pmdp_invalidate()->pmd_mkinvalid(), which clears the PRESENT bit and PROT_NONE bit/READ bit, if the PMD is read-only, then the PAGE_LEAF property is also cleared, which results in pmd_present() return false. 2. When migrating, the swap entry only clear the PRESENT bit and PROT_NONE bit/READ bit, the W/X bit may be set, so _PAGE_LEAF may be true which results in pmd_present() return true. Solution: Adjust PROT_NONE bit from READ to GLOBAL bit can satisfy the above rules: 1. GLOBAL bit has no other meanings, not like the R/W/X bit, which is also relative with _PAGE_LEAF property. 2. GLOBAL bit is at bit 5, making swap entry start from bit 6, bit 0-5 are zero, which means the PRESENT, PROT_NONE, and PAGE_LEAF are all false, then the pmd_present() and pmd_trans_huge() return false when in migration/swap. Signed-off-by:
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hasheddan authored
Fixes misspelling of guaranteed in comment describing why fetching fence is guaranteed to work when switching to kernel page tables. Signed-off-by:
hasheddan <georgedanielmangum@gmail.com> Signed-off-by:
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- 06 Jan, 2022 21 commits
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Palmer Dabbelt authored
It's been a while since cleaning up the defconfigs, so I manually checked up on each change. This found a handful of minor issues, which have been fixed in-line.
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Palmer Dabbelt authored
The "k210_generic" DT has been the default in Kconfig since 67d96729 ("riscv: Update Canaan Kendryte K210 device tree"), so drop it from the defconfigs to avoid diff with savedefconfig. Reviewed-by:
Anup Patel <anup@brainfault.org> Signed-off-by:
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Palmer Dabbelt authored
We've always had CONFIG_EFI as "def_bool y" so this has always been redundant. It's removed by savedefconfig, so drop it to keep things clean. Reviewed-by:
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Palmer Dabbelt authored
As of ab7fbad0 ("riscv: Fix unmet direct dependencies built based on SOC_VIRT") we select CONFIG_POWER_RESET=y along with CONFIG_SOC_VIRT, which is already in defconfig. This make setting CONFIG_POWER_RESET in the defconfigs redundant, so remove it to remain consistent with savedefconfig. Reviewed-by:
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Palmer Dabbelt authored
This should have no functional change, it just sorts CONFIG_BLK_DEV_BSG the same way savedefconfig does. Reviewed-by:
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Palmer Dabbelt authored
This should have no functional change, it just sorts CONFIG_SURFACE_PLATFORMS the same way savedefconfig does. Reviewed-by:
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Palmer Dabbelt authored
This should have no functional change, it just sorts CONFIG_MMC the same way savedefconfig does. This only touches the rv64 defconfig because rv32_defconfig was already sorted correctly. Reviewed-by:
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Palmer Dabbelt authored
This should have no functional change, it just sorts CONFIG_PTP_1588_CLOCK the same way savedefconfig does. This only touches the rv64 defconfig because rv32_defconfig was already sorted correctly. Reviewed-by:
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Palmer Dabbelt authored
This should have no functional change, it just sorts CONFIG_SOC_POLARFIRE the same way savedefconfig does. Reviewed-by:
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Palmer Dabbelt authored
This should have no functional change, it just sorts CONFIG_SYSFS_SYSCALL the same way savedefconfig does. Reviewed-by:
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Palmer Dabbelt authored
This should have no functional change, it just sorts CONFIG_BPF_SYSCALL the same way savedefconfig does. Reviewed-by:
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Palmer Dabbelt authored
For non-relocatable kernels we need to be able to link the kernel at approximately PAGE_OFFSET, thus requiring medany (as medlow requires the code to be linked within 2GiB of 0). The inverse doesn't apply, though: since medany code can be linked anywhere it's fine to link it close to 0, so we can support the smaller memory config. Fixes: de5f4b8f ("RISC-V: Define MAXPHYSMEM_1GB only for RV32") Reviewed-by:
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Palmer Dabbelt authored
We have CONFIG_FRAMEBUFFER_CONSOLE=y in the defconfigs, but that depends on CONFIG_FB so it's not actually getting set. I'm assuming most users on real systems want a framebuffer console, so this enables CONFIG_FB to allow that to take effect. Fixes: 33c57c0d ("RISC-V: Add a basic defconfig") Reviewed-by:
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Kefeng Wang authored
After commit 1355c31e ("asm-generic: pgalloc: provide generic pmd_alloc_one() and pmd_free_one()"), the main part to support PMD split page table lock is in asm-generic/pgalloc.h. The only change is add pgtable_pmd_page_ctor() into alloc_pmd_late(), then we could enable ARCH_ENABLE_SPLIT_PMD_PTLOCK for RV64. Reviewed-by:
Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by:
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Alexandre Ghiti authored
We used to define VMALLOC_END equal to the start of the next region *minus one* which is inconsistent with the use of this define in the core code (for example, see the definitions of VMALLOC_TOTAL and is_vmalloc_addr). And then make the definition of VMEMMAP_END consistent with VMALLOC_END and all other regions actually. Signed-off-by:
Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by:
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Palmer Dabbelt authored
Similar as other architectures such as arm64, x86 and so on, use offsets relative to the exception table entry values rather than absolute addresses for both the exception locationand the fixup. And recently, arm64 and x86 remove anonymous out-of-line fixups, we want to acchieve the same result.
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Jisheng Zhang authored
These are no longer necessary now that we have a more standard extable mechanism. Signed-off-by:
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Jisheng Zhang authored
Inspired by commit 2e77a62c ("arm64: extable: add a dedicated uaccess handler"), do similar to riscv to add a dedicated uaccess exception handler to update registers in exception context and subsequently return back into the function which faulted, so we remove the need for fixups specialized to each faulting instruction. Signed-off-by:
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Jisheng Zhang authored
This defines the mapping from ABI names to X registers. Signed-off-by:
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Jisheng Zhang authored
This is a riscv port of commit d6e2cc56 ("arm64: extable: add `type` and `data` fields"). Signed-off-by:
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Jisheng Zhang authored
This is a riscv port of commit 819771cc ("arm64: extable: consolidate definitions"). Signed-off-by:
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