- 20 Feb, 2023 7 commits
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Ville Syrjälä authored
The DSI code has some local hacks to program TRANS_VBLANK on TGL+ (ICL DSI transcoders didn't have this register). That will not work when we need to start using the delayed vblank (for DSB purposes). Too lazy to figure out what the is going on there, so just sprinkle FIXMEs in the hopes someone else will spot them eventually. v2: Only TRANS_{HBLANK,SET_CONTEXT_LATENCY} still no not exist for DSI transcoders, only TRANS_VBLANK Signed-off-by:Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-12-ville.syrjala@linux.intel.comAcked-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
On TGL VBLANK.VBLANK_START was the mechanism by which we can delay the pipe's internal vblank in relation to the transcoder's vblank. On ADL+ that no longer does anything. Instead we must now use the new TRANS_SET_CONTEXT_LATENCY register. Program it accordingly. And since VBLANK.VBLANK_START is no longer used by the hardware on ADL+ let's just zero it out to make it stand out in register dumps. Seeing the zeroed value should hopefully remind people to check the other register instead. Signed-off-by:
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Ville Syrjälä authored
If we have no LUTs to load there is no point in setting up the DSB command buffer. Signed-off-by:
Animesh Manna <animesh.manna@intel.com>
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Ville Syrjälä authored
We'll be wanting to start the DSB from the vblank evasion critical section so printk()s are a big nono. Get rid of the debug print. Signed-off-by:
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Ville Syrjälä authored
Allow the caller to ask for the DSB commands to execute during vblank. Signed-off-by:
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Ville Syrjälä authored
Add definitions for more DSB registers. Less annoying spec trawling when working on the DSB code. Signed-off-by:
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Ville Syrjälä authored
The PSR code has no business mucking around with the vblank delay. Currently nothing that depends on knowing the exact vblank start scanline (eg. vblank evasion) is aware of this and so will not work correctly. The w/a seems to be for pre-production hw only, so let's just nuke it. Signed-off-by:
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- 17 Feb, 2023 11 commits
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Ville Syrjälä authored
Define the contents of the transcoder timing registers using REG_GENMASK() & co. For ease of maintenance let's just define the bitmasks with the full 16bit width (also used by the current hand rolled stuff) even though not all bits are actually used. None of the unsued bits have ever contained anything. Jani spotted that the CRT load detection code did use narrower bitmasks, so that is now going to change. But that is fine since any garbage in the high bits would have been caught by the state checker that always used the full 16bit masks. Signed-off-by:
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Ville Syrjälä authored
Clean up the eyesore in intel_get_transcoder_timings() a bit by adding a local 'adjusted_mode' variable. Signed-off-by:
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Ville Syrjälä authored
On TGL+ the normal "start of vblank" interrupt is the pipe's (potentially delayed) version. Add the new bit for the transcoder's "unmodified" vblank so I don't have to dig it out from bspec every time. Signed-off-by:
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Ville Syrjälä authored
With the delayed vblank we need to start knowing where the blanking periods start. So let's start dumping out also the blanking start/end timings. And while at it let's try to make that huge list of numbers somewhat legible by indicating what each value means. Also drop the 'type' since that doesn't really mean anything for the crtc_ timings. Signed-off-by:
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Ville Syrjälä authored
Rename PIPECONF to TRANSCONF to make it clear what it actually applies to. While the usual convention is to pick the earliers name I think in this case it's more clear to use the later name. Especially as even the register offset is in the wrong range (0x70000 vs. 0x60000) and thus makes it look like this is per-pipe. There is one place in gvt that's doing something with TRANSCONF while iterating with for_each_pipe(). So that might not be doing the right thing for TRANSCODER_EDP, dunno. Not knowing what it does I left it as is to avoid breakage. Signed-off-by:
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Ville Syrjälä authored
Name the CPU transcoder timing registers TRANS_FOO rather than just FOO. This is the modern name, after the pipe/transcoder split happened. Makes it a bit more obvious whether you pass in a pipe or a transcoder. PIPESRC is a bit special as it's a pipe register, even though it lives in the transcoder registers range (0x60000 instead of 0x70000). And BCLRPAT I suppose is a transcoder register (since it has something to do with the timing generator), but it doesn't even exist after gen4 so I left it to use the only name it ever had in bspec. And while at it let's pass in the correct enum in few more places why don't we. Although in all those places the distinction doesn't matter. Signed-off-by:
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Ville Syrjälä authored
Use an early return to get rid of the extra indentation level in intel_ddi_{enable,disable}_transcoder_clock(). Also unify the platform handling in between the two while at it. Signed-off-by: -
Ville Syrjälä authored
What intel_ddi_{enable,disable}_pipe_clock() actually do is enable the clock to the transcoder, not the pipe. Rename accordingly. Signed-off-by: -
Ville Syrjälä authored
SKL/derivatives have DDI E but no AUX E, so we need to pick another aux ch as the platform default. DDI E is more or less the other half of DDI A, so we pick AUX A. In all other cases we should have a corresponding aux ch for each DDI. Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com>
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Ville Syrjälä authored
Use encoder->name rather than port_name() in the debug messages so that they actually make more sense. Signed-off-by:
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Ville Syrjälä authored
Restructure intel_bios_port_aux_ch() to resemble the ddc_pin counterpart, where the intel_bios.c stuff only deals with the child device definition, and the platform default will come from elsewhere. This requires the introduction of AUX_CH_NONE as the value 0 is already taken to mean AUX_CH_A. v2: Sort includes alphabetically (Ankit) vCould we ask them to do a BIOS fix for all of them so that we wouldn't keep getting these bug reports for each model separately? Signed-off-by:
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- 16 Feb, 2023 22 commits
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Ashutosh Dixit authored
Previous documentation suggested that the PL1 power limit is always enabled in HW. However we now find this not to be the case on some platforms (such as ATSM). Therefore enable the PL1 power limit (by setting the enable bit) when writing the PL1 limit value to HW. Bspec: 51864 Signed-off-by:
Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Ashutosh Dixit authored
hwm_field_scale_and_write has a single caller hwm_power_write and is specific to hwm_power_write but makes it appear that it is a general function which can have multiple callers. Replace the function with hwm_power_max_write which is specific to hwm_power_write and use that in future patches where the function needs to be extended. Signed-off-by:
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Ville Syrjälä authored
Switch a lot of the intel_bios_foo() stuff to just accept the devdata (VBT child device info) directly, instead of taking detours via vbt.ports[]. Also unify the function naming scheme. v2: Drop the redundant "encoder" from the dp/hdmi specific functions Signed-off-by:
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Ville Syrjälä authored
Most of the .fb_create() failure paths are annotated but there are a few that seem capable of failing silently (well, higher level code should print something, just not anything actually useful). Drop a few more hints into the log to aid in debugging. Signed-off-by:
Matt Roper <matthew.d.roper@intel.com>
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Ville Syrjälä authored
We are failing to free the already allocated DPT if the final drm_framebuffer_init() fails. That would require idr_alloc() to fail, so not very likely, but let's add the cleanup code anyway. Signed-off-by:
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Ville Syrjälä authored
Do the ELD hexdumps only up to the last differing byte. The rest is typically all zeroes anyway so not much point in dumping it. Couldn't find anything for memcmp_diff_len() so rolled my own. v2: Use semantics and function name suggested by Jani Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Ville Syrjälä authored
With multi panel machines becoming more prominent it's also important to know which connector's backlight we're talking about. Include that information in all the backlight debug/error messages. Signed-off-by:
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Mavroudis Chatzilaridis authored
This laptop uses inverted backlight PWM. Thus, without this quirk, backlight brightness decreases as the brightness value increases and vice versa. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8013 Cc: stable@vger.kernel.org Signed-off-by:
Mavroudis Chatzilaridis <mavchatz@protonmail.com> Reviewed-by:
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Andrzej Hajda authored
The helper makes the code more compact and readable. Signed-off-by:
Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by:
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Andrzej Hajda authored
The helper makes the code more compact and readable. Signed-off-by:
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Andrzej Hajda authored
The helper makes the code more compact and readable. Signed-off-by:
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Andrzej Hajda authored
The helper makes the code more compact and readable. Signed-off-by:
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Andrzej Hajda authored
The helper makes the code more compact and readable. Signed-off-by:
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Andrzej Hajda authored
The helper makes the code more compact and readable. Signed-off-by:
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Andrzej Hajda authored
The helper makes the code more compact and readable. Signed-off-by:
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Andrzej Hajda authored
The helper makes the code more compact and readable. Signed-off-by:
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Jani Nikula authored
Disabling ILK+ watermarks on failure to read the watermark levels dates back to 2010 and commit 7f8a8569 ("drm/i915: Add the support of memory self-refresh on Ironlake"), with no explanations, and it's been copied and modified from that ever since. Finally drop it. If the value are actually zero, the ilk_compute_*_wm() functions should handle it gracefully. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by:
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Jani Nikula authored
The file was never really about pm types, and now it's even more obvious. Move under display as intel_wm_types.h. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Follow the new convention of placing debugfs with the code. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
The sanitization should be limited to PCH split platforms up to display version 8. Warn and bail out otherwise. Signed-off-by:
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Jani Nikula authored
Move sanitize_watermarks() to i9xx_wm.[ch] and rename as ilk_wm_sanitize(). The slightly unfortunate downside is having to expose intel_atomic_check() from intel_display.c, but this declutters intel_display.c nicely. v2: - Move to i9xx_wm.[ch] instead of intel_wm.[ch] (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Stanislav Lisovskiy authored
There was a specific SW workaround requested, which should prevent some watermark issues happening, which requires copying highest enabled wm level to those disabled wm levels(bit 31 is of course still needs to be cleared). This is related to different subsystems like PSR and others, which may still consult a low power wm values ocassionally, despite those are disabled. For that reason we need to keep sane values in correspondent registers, even when those are disabled. HSDES: 22016115093 v2: Remove redundant WA for ICL and extend this WA for all platforms starting from SKL, as it seems that we needed this anyway on all of those(Ville Syrjälä) Signed-off-by:Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by:
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