- 01 Sep, 2024 1 commit
-
-
Konrad Dybcio authored
There are some cases, such as the one uncovered by Commit 46d4efcc ("drm/msm/a6xx: Avoid a nullptr dereference when speedbin setting fails") where msm_gpu_cleanup() : platform_set_drvdata(gpu->pdev, NULL); is called on gpu->pdev == NULL, as the GPU device has not been fully initialized yet. Turns out that there's more than just the aforementioned path that causes this to happen (e.g. the case when there's speedbin data in the catalog, but opp-supported-hw is missing in DT). Assigning msm_gpu->pdev earlier seems like the least painful solution to this, therefore do so. Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/602742/Signed-off-by:
Rob Clark <robdclark@chromium.org>
-
- 30 Aug, 2024 16 commits
-
-
Aleksandr Mishin authored
In adreno_request_fw() when debugging information is printed to the log after firmware load, an incorrect filename is printed. 'newname' is used instead of 'fwname', so prefix "qcom/" is being added to filename. Looks like "copy-paste" mistake. Fix this mistake by replacing 'newname' with 'fwname'. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 2c41ef1b ("drm/msm/adreno: deal with linux-firmware fw paths") Signed-off-by:
Aleksandr Mishin <amishin@t-argos.ru> Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/602382/Signed-off-by:
-
Connor Abbott authored
Make it match the MDSS settings for sc8180x and downstream. Note that without the previous commit that exposes the value of macrotile_mode to mesa, this will break mesa which expects the legacy default value of 0. Therefore we do *not* want to backport it. Signed-off-by:
Connor Abbott <cwabbott0@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/607398/Signed-off-by:
-
Connor Abbott authored
This adds extra parameters that affect UBWC tiling that will be used by the Mesa implementation of VK_EXT_host_image_copy. Signed-off-by:
-
Connor Abbott authored
According to downstream we should be setting RBBM_NC_MODE_CNTL to a non-default value on a663 and a680, we don't support a663 and on a680 we're leaving it at the wrong (suboptimal) value. Just set it on all GPUs. Similarly, plumb through level2_swizzling_dis which will be necessary on a663. ubwc_mode is expanded and renamed to ubwc_swizzle to match the name on the display side. Similarly macrotile_mode should match the display side. Signed-off-by:
-
Connor Abbott authored
Update to Mesa commit 36a13d2b3b0 ("freedreno: fix a7xx perfcntr countables"). Signed-off-by: -
Connor Abbott authored
This was missed because we weren't using the a750-specific indexed regs. Fixes: f3f8207d ("drm/msm: Add devcoredump support for a750") Signed-off-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/607394/Signed-off-by:
-
Connor Abbott authored
This was missed thanks to the family mixup fixed in the previous commit. Fixes: f3f8207d ("drm/msm: Add devcoredump support for a750") Signed-off-by:
-
Connor Abbott authored
With a7xx, we need to import a new header for each new generation and switch to a different list of registers, instead of making backwards-compatible changes. Using the helpers inadvertently made a750 use the a740 list of registers, instead use the family directly to fix this. Fixes: f3f8207d ("drm/msm: Add devcoredump support for a750") Signed-off-by:
-
Richard Acayan authored
The Adreno A615 is used in SDM670. Add an entry to support it. Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/607238/Signed-off-by:
-
Eugene Lepshy authored
According to downstream, A642L's speedbin is 129 and uses 4 as index Signed-off-by:
Eugene Lepshy <fekz115@gmail.com> Signed-off-by:
Danila Tikhonov <danila@jiaxyga.com> Reviewed-by:
-
Rob Clark authored
This was added in commit ec446d09 ("drm/msm: call drm_atomic_helper_suspend() and drm_atomic_helper_resume()"), but unused since commit ca8199f1 ("drm/msm/dpu: ensure device suspend happens during PM sleep") which switched to drm_mode_config_helper_suspend()/ drm_mode_config_helper_resume().. Signed-off-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/607746/
-
Laurent Pinchart authored
The msm_atomic_state_clear() and msm_atomic_state_free() functions are declared but never defined. Remove their prototypes. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by:
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Patchwork: https://patchwork.freedesktop.org/patch/610618/Signed-off-by:
-
Li Zetao authored
Use kvmemdup instead of kvmalloc() + memcpy() to simplify the code. No functional change intended. Signed-off-by:
Li Zetao <lizetao1@huawei.com> Reviewed-by:
-
Dave Airlie authored
Merge tag 'drm-intel-next-2024-08-29' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Cross-driver (xe-core) Changes: - Require BMG scanout buffers to be 64k physically aligned (Maarten) Core (drm) Changes: - Introducing Xe2 ccs modifiers for integrated and discrete graphics (Juha-Pekka) Driver Changes: - General cleanup and more work moving towards intel_display isolation (Jani) - New display workaround (Suraj) - Use correct cp_irq_count on HDCP (Suraj) - eDP PSR fix when CRC is enabled (Jouni) - Fix DP MST state after a sink reset (Imre) - Fix Arrow Lake GSC firmware version (John) - Use chained DSBs for LUT programming (Ville) Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ZtCC0lJ0Zf3MoSdW@intel.com
-
https://gitlab.freedesktop.org/drm/xe/kernelDave Airlie authored
UAPI Changes: - Fix OA format masks which were breaking build with gcc-5 Cross-subsystem Changes: Driver Changes: - Use dma_fence_chain_free in chain fence unused as a sync (Matthew Brost) - Refactor hw engine lookup and mmio access to be used in more places (Dominik, Matt Auld, Mika Kuoppala) - Enable priority mem read for Xe2 and later (Pallavi Mishra) - Fix PL1 disable flow in xe_hwmon_power_max_write (Karthik) - Fix refcount and speedup devcoredump (Matthew Brost) - Add performance tuning changes to Xe2 (Akshata, Shekhar) - Fix OA sysfs entry (Ashutosh) - Add first GuC firmware support for BMG (Julia) - Bump minimum GuC firmware for platforms under force_probe to match LNL and BMG (Julia) - Fix access check on user fence creation (Nirmoy) - Add/document workarounds for Xe2 (Julia, Daniele, John, Tejas) - Document workaround and use proper WA infra (Matt Roper) - Fix VF configuration on media GT (Michal Wajdeczko) - Fix VM dma-resv lock (Matthew Brost) - Allow suspend/resume exec queue backend op to be called multiple times (Matthew Brost) - Add GT stats to debugfs (Nirmoy) - Add hwconfig to debugfs (Matt Roper) - Compile out all debugfs code with ONFIG_DEUBG_FS=n (Lucas) - Remove dead kunit code (Jani Nikula) - Refactor drvdata storing to help display (Jani Nikula) - Cleanup unsused xe parameter in pte handling (Himal) - Rename s/enable_display/probe_display/ for clarity (Lucas) - Fix missing MCR annotation in couple of registers (Tejas) - Fix DGFX display suspend/resume (Maarten) - Prepare exec_queue_kill for PXP handling (Daniele) - Fix devm/drmm issues (Daniele, Matthew Brost) - Fix tile and ggtt fini sequences (Matthew Brost) - Fix crashes when probing without firmware in place (Daniele, Matthew Brost) - Use xe_managed for kernel BOs (Daniele, Matthew Brost) - Future-proof dss_per_group calculation by using hwconfig (Matt Roper) - Use reserved copy engine for user binds on faulting devices (Matthew Brost) - Allow mixing dma-fence jobs and long-running faulting jobs (Francois) - Cleanup redundant arg when creating use BO (Nirmoy) - Prevent UAF around preempt fence (Auld) - Fix display suspend/resume (Maarten) - Use vma_pages() helper (Thorsten) - Calculate pagefault queue size (Stuart, Matthew Auld) - Fix missing pagefault wq destroy (Stuart) - Fix lifetime handling of HW fence ctx (Matthew Brost) - Fix order destroy order for jobs (Matthew Brost) - Fix TLB invalidation for media GT (Matthew Brost) - Document GGTT (Rodrigo Vivi) - Refactor GGTT layering and fix runtime outer protection (Rodrigo Vivi) - Handle HPD polling on display pm runtime suspend/resume (Imre, Vinod) - Drop unrequired NULL checks (Apoorva, Himal) - Use separate rpm lockdep map for non-d3cold-capable devices (Thomas Hellström) - Support "nomodeset" kernel command-line option (Thomas Zimmermann) - Drop force_probe requirement for LNL and BMG (Lucas, Balasubramani) Signed-off-by:
-
Dave Airlie authored
Merge tag 'drm-misc-next-2024-08-29' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.12: UAPI Changes: devfs: - support device numbers up to MINORBITS limit Core Changes: ci: - increase job timeout devfs: - use XArray for minor ids displayport: - mst: GUID improvements docs: - add fixes and cleanups panic: - optionally display QR code Driver Changes: amdgpu: - faster vblank disabling - GUID improvements gm12u320 - convert to struct drm_edid host1x: - fix syncpoint IRQ during resume - use iommu_paging_domain_alloc() imx: - ipuv3: convert to struct drm_edid omapdrm: - improve error handling panel: - add support for BOE TV101WUM-LL2 plus DT bindings - novatek-nt35950: improve error handling - nv3051d: improve error handling - panel-edp: add support for BOE NE140WUM-N6G; revert support for SDC ATNA45AF01 - visionox-vtdr6130: improve error handling; use devm_regulator_bulk_get_const() renesas: - rz-du: add support for RZ/G2UL plus DT bindings sti: - convert to struct drm_edid tegra: - gr3d: improve PM domain handling - convert to struct drm_edid Signed-off-by:
-
- 29 Aug, 2024 23 commits
-
-
Ville Syrjälä authored
In order to better handle the necessary DSB DEwake tricks let's switch over to using a chained DSB for the actual LUT programming. The CPU will start 'dsb_color_commit', which in turn will start the chained 'dsb_color_vblank'. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240624191032.27333-15-ville.syrjala@linux.intel.comReviewed-by:
Animesh Manna <animesh.manna@intel.com>
-
Ville Syrjälä authored
We'll soon utilize several DSBs during the commit. To that end rename the current crtc_state->dsb to crtc_state->dsb_color_vblank to better reflect its role (color managemnent stuff programmed during vblank). Signed-off-by:
-
Ville Syrjälä authored
In order to avoid the DSB keeping the DEwake permanently asserted we must clear DSB_PMCTRL_2.DSB_FORCE_DEWAKE once we are done. For good measure do the same for DSB_PMCTRL.DSB_ENABLE_DEWAKE. Experimentally this doens't seem to be actually necessary (unlike with DSB_FORCE_DEWAKE). That is, the DSB_ENABLE_DEWAKE doesn't seem to do anything whenever the DSB is not active. But I'd hate to waste a ton of power in case there I'm wrong and there is some way DEwake could remaing asserted. One extra register write is a small price to pay for some peace of mind. Signed-off-by:
-
Ville Syrjälä authored
Allow intel_dsb_chain() to start the chained DSB at start of the undelaye vblank. This is slightly more involved than simply setting the bit as we must use the DEwake mechanism to eliminate pkgC latency. And DSB_ENABLE_DEWAKE itself is problematic in that it allows us to configure just a single scanline, and if the current scanline is already past that DSB_ENABLE_DEWAKE won't do anything, rendering the whole thing moot. The current workaround involves checking the pipe's current scanline with the CPU, and if it looks like we're about to miss the configured DEwake scanline we set DSB_FORCE_DEWAKE to immediately assert DEwake. This is somewhat racy since the hardware is making progress all the while we're checking it on the CPU. We can make things less racy by chaining two DSBs and handling the DSB_FORCE_DEWAKE stuff entirely without CPU involvement: 1. CPU starts the first DSB immediately 2. First DSB configures the second DSB, including its dewake_scanline 3. First DSB starts the second w/ DSB_WAIT_FOR_VBLANK 4. First DSB asserts DSB_FORCE_DEWAKE 5. First DSB waits until we're outside the dewake_scanline-vblank_start window 6. First DSB deasserts DSB_FORCE_DEWAKE That will guarantee that the we are fully awake when the second DSB starts to actually execute. Signed-off-by:
-
Ville Syrjälä authored
In order to handle the DEwake tricks without involving the CPU we need a mechanism by which one DSB can start another one. Add a basic function to do so. We'll extend it later with additional code to actually deal with DEwake. Signed-off-by:
-
Ville Syrjälä authored
Add functions to emit a DSB scanline window wait instructions. We can either wait for the scanline to be IN the window or OUT of the window. The hardware doesn't handle wraparound so we must manually deal with it by swapping the IN range to the inverse OUT range, or vice versa. Also add a bit of paranoia to catch the edge case of waiting for the entire frame. That doesn't make sense since an IN wait would be a nop, and an OUT wait would imply waiting forever. Most of the time this also results in both scanline ranges (original and inverted) to have lower=upper+1 which is nonsense from the hw POV. For now we are only handling the case where the scanline wait happens prior to latching the double buffered registers during the commit (which might change the timings due to LRR/VRR/etc.) Signed-off-by:
-
Ville Syrjälä authored
Adjust the code that determines the correct DSB_CHICKEN value to be usable for use within DSB commands themselves. Ie. precompute it based on our knowledge of what the hardware state (VRR vs. not mainly) will be at the time of the commit. Signed-off-by:
-
Ville Syrjälä authored
When determining various scanlines for DSB use we should take into account whether VRR is active at the time when the DSB uses said scanline information. For now all DSB scanline usage occurs prior to the actual commit, so we only need to care about the state of VRR at that time. I've decided to move intel_crtc_scanline_to_hw() in its entirety to the DSB code as it will also need to know the actual state of VRR in order to do its job 100% correctly. TODO: figure out how much of this could be moved to some more generic place and perhaps be shared with the CPU vblank evasion code/etc... Signed-off-by: -
Ville Syrjälä authored
Currently we calculate the DEwake scanline based on the delayed vblank start, while in reality it should be computed based on the undelayed vblank start (as that is where the DSB actually starts). Currently it doesn't really matter as we don't have any vblank delay configured, but that may change in the future so let's be accurate in what we do. We can also remove the max() as intel_crtc_scanline_to_hw() can deal with negative numbers, which there really shouldn't be anyway. Signed-off-by:
-
Ville Syrjälä authored
Relocate intel_dsb_dewake_scanline() and dsb_chicken() upwards in the file. I need to reuse these while emitting DSB commands, and I'd like to keep the DSB command emission stuff more or less grouped together in the file. Also drop the intel_ prefix from intel_dsb_dewake_scanline() since it's all internal stuff and thus doesn't need so much namespacing. Signed-off-by:
-
Ville Syrjälä authored
Currently we switch from out software idea of a scanline to the hw's idea of a scanline during the commit phase in _intel_dsb_commit(). While that is slightly easier due to fastsets fiddling with the timings, we'll also need to generate proper hw scanline numbers already when emitting DSB scanline wait instructions. So this approach won't do in the future. Switch to hw scanline numbers earlier. Also intel_dsb_dewake_scanline() itself already makes some assumptions about VRR that don't take into account VRR toggling during fastsets, so technically delaying the sw->hw conversion doesn't even help us. The other reason for delaying the conversion was that we are using intel_get_crtc_scanline() during intel_dsb_commit() which gives us the current sw scanline. But this is pretty low level stuff anyway so just using raw PIPEDSL reads seems fine here, and that of course gives us the hw scanline directly, reducing the need to do so many conversions. v2: Return the non-hw scanline from intel_dsb_dewake_scanline() Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
-
Ville Syrjälä authored
Enable all DSB error/fault interrupts so that we can see if anything goes terribly wrong. v2: Pass intel_display to DISPLAY_VER() (Jani) Drop extra '/' from drm_err() for consistency v3: Reorder the irq handler a bit Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: -
Jani Nikula authored
Prefer the struct drm_edid based functions for allocating the EDID and updating the connector. Reviewed-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/c31c3afa883a3321345608c480c26161b638a83e.1724348429.git.jani.nikula@intel.comSigned-off-by:
-
Jani Nikula authored
Prefer the struct drm_edid based functions for storing the EDID and updating the connector. Reviewed-by:
-
Jani Nikula authored
Prefer the struct drm_edid based functions for reading the EDID and updating the connector. Acked-by:
Thierry Reding <treding@nvidia.com> Reviewed-by:
-
Jani Nikula authored
Prefer the struct drm_edid based functions for reading the EDID and updating the connector. The functional change is that the CEC physical address gets invalidated when the EDID could not be read. v2: Use drm_edid_read() instead of drm_edid_read_ddc() (Sima) Reviewed-by:
-
Ville Syrjälä authored
On ilk/snb the pipe may be configured to place the LUT before or after the CSC depending on various factors, but as there is only one LUT (no split mode like on IVB+) we only advertise a gamma_lut and no degamma_lut in the uapi to avoid confusing userspace. This can cause a problem during readout if the VBIOS/GOP enabled the LUT in the pre CSC configuration. The current code blindly assigns the results of the readout to the degamma_lut, which will cause a failure during the next atomic_check() as we aren't expecting anything to be in degamma_lut since it's not visible to userspace. Fix the problem by assigning whatever LUT we read out from the hardware into gamma_lut. Cc: stable@vger.kernel.org Fixes: d2559299 ("drm/i915: Make ilk_read_luts() capable of degamma readout") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11608Signed-off-by:
Uma Shankar <uma.shankar@intel.com>
-
Abhishek Tamboli authored
Replace deprecated 'mipi_dsi_dcs_write_seq()' macro to 'mipi_dsi_dcs_write_seq_multi' macro in panel_nv3051d_init_sequence function. Signed-off-by:
Abhishek Tamboli <abhishektamboli9@gmail.com> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240827152504.30586-1-abhishektamboli9@gmail.comSigned-off-by:
-
Tejas Vipin authored
Changes the novatek-nt35950 panel to use multi style functions for improved error handling. Reviewed-by:
Tejas Vipin <tejasvipin76@gmail.com> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240828182210.565861-1-tejasvipin76@gmail.comSigned-off-by:
-
Neil Armstrong authored
Switch to devm_regulator_bulk_get_const() to stop setting the supplies list in probe(), and move the regulator_bulk_data struct in static const. Reviewed-by:
-
Neil Armstrong authored
Make usage of the new _multi() mipi_dsi functions instead of the deprecated macros, improving error handling and printing. bloat-o-meter gives a 12% gain on arm64: Function old new delta visionox_vtdr6130_unprepare 208 204 -4 visionox_vtdr6130_prepare 1192 896 -296 Total: Before=2348, After=2048, chg -12.78% Reviewed-by:
-
Jani Nikula authored
Instead of just smashing jiffies into a GUID, use guid_gen() to generate RFC 4122 compliant GUIDs. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240812122312.1567046-3-jani.nikula@intel.comSigned-off-by:
-
Jani Nikula authored
Instead of just smashing jiffies into a GUID, use guid_gen() to generate RFC 4122 compliant GUIDs. Reviewed-by:
-
