- 18 Jul, 2018 40 commits
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having PLAT_SPEAR, ARCH_NOMADIK, ARCH_U8500 or MACH_U300 enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com>
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Boris Brezillon authored
uintptr_t should be used when casting a pointer to an unsigned int so that the code compiles without warnings even on 64-bit architectures. This is needed if we want to allow selection of this driver when COMPILE_TEST=y. Signed-off-by:
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Boris Brezillon authored
We want to allow this driver to be selected when COMPILE_TEST=y, this means the driver can be compiled for any arch, including MIPS. When compiling this driver for MIPS, we end up with a collision on the 'PC' macro definition (also defined in arch/mips/include/asm/ptrace.h). Prefix the fsmc one with FSMC_ to avoid this problem. Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARCH_SUNXI enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
Fixes the following smatch warning: drivers/mtd/nand/raw/sunxi_nand.c:551 sunxi_nfc_read_byte() error: uninitialized symbol 'ret'. Signed-off-by:
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Boris Brezillon authored
Fixes the "warning: large integer implicitly truncated to unsigned type [-Woverflow]" warning when compiled for x86. This is needed in order to allow compiling this driver when COMPILE_TEST=y. Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARCH_DAVINCI or ARCH_KEYSTONE enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Miquel Raynal authored
Rules about Kconfig are simple but in the raw NAND directory indentation is somehow archaic. Fix the indentation in the whole file. Signed-off-by: -
Boris Brezillon authored
uintptr_t should be used when casting a pointer to an unsigned int so that the code compiles without warnings even on 64-bit architectures. This is needed if we want to allow selection of this driver when COMPILE_TEST=y. Reported-by:
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Boris Brezillon authored
There is no point in doing this sort of conversion since we can replace |= by += operations which are perfectly valid on pointers. This is done in preparation of COMPILE_TEST addition to the NAND_DAVINCI Kconfig entry, since building for x86 generates several warnings because of inappropriate u32 <-> void * conversions (pointers are 64-bit large on x86_64). Reported-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARCH_AT91 enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
gen_pool_dma_alloc() return type is void *, while internally, the memory region exposed by the sram driver has been mapped with ioremap(). Add a void * to void __iomem * cast to make sparse happy. Signed-off-by:
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Boris Brezillon authored
When casting a pointer to an unsigned int, uintptr_t should be used to cope with the pointer size differences between 32-bit and 64-bit architectures. This is needed if we want to allow compilation of this driver when COMPILE_TEST=y. Reported-by:
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Boris Brezillon authored
Modern NAND controller drivers implement ->exec_op() instead of ->cmdfunc(), make sure we don't end up with a NULL pointer dereference when hynix_nand_reg_write_op() is called. Fixes: 8878b126 ("mtd: nand: add ->exec_op() implementation") Cc: <stable@vger.kernel.org> Signed-off-by:
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Daniel Mack authored
Don't keep an error-pointer around in the private struct. If this optional clock can't be obtained, simply set the pointer to NULL instead so we can use clk_prepare_enable() on it without further checks, Signed-off-by:
Daniel Mack <daniel@zonque.org> Signed-off-by:
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Daniel Mack authored
The comment in marvell_nfc_select_chip() about ndtr0 and ndtr1 didn't reflect what the driver was doing. The values of NDTR0 and NDTR1 are read from the registers at probe time and a copy is retained in 'struct marvell_nand_chip'. If keep-config is set in the DT properties, there are no other writers of these timing variables so they can safely be used when the chip is selected. As suggested by Miquel Raynal, simply remove the comment. Signed-off-by:
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Daniel Mack authored
This patch restores the suspend and resume hooks that the old driver used to have. Apart from stopping and starting the clocks, the resume callback also nullifies the selected_chip pointer, so the next command that is issued will re-select the chip and thereby restore the timing registers. Factor out some code from marvell_nfc_init() into a new function marvell_nfc_reset() and also call it at resume time to reset some registers that don't retain their contents during low-power mode. Without this patch, a PXA3xx based system would cough up an error similar to the one below after resume. [ 44.660162] marvell-nfc 43100000.nand-controller: Timeout waiting for RB signal [ 44.671492] ubi0 error: ubi_io_write: error -110 while writing 2048 bytes to PEB 102:38912, written 0 bytes [ 44.682887] CPU: 0 PID: 1417 Comm: remote-control Not tainted 4.18.0-rc2+ #344 [ 44.691197] Hardware name: Marvell PXA3xx (Device Tree Support) [ 44.697111] Backtrace: [ 44.699593] [<c0106458>] (dump_backtrace) from [<c0106718>] (show_stack+0x18/0x1c) [ 44.708931] r7:00000800 r6:00009800 r5:00000066 r4:c6139000 [ 44.715833] [<c0106700>] (show_stack) from [<c0678a60>] (dump_stack+0x20/0x28) [ 44.724206] [<c0678a40>] (dump_stack) from [<c0456cbc>] (ubi_io_write+0x3d4/0x630) [ 44.732925] [<c04568e8>] (ubi_io_write) from [<c0454428>] (ubi_eba_write_leb+0x690/0x6fc) ... Fixes: 02f26ecf ("mtd: nand: add reworked Marvell NAND controller driver") Cc: stable@vger.kernel.org Signed-off-by:
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Fabio Estevam authored
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by:
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Fabio Estevam authored
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by:
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Boris Brezillon authored
None of the board files are overloading those hooks, so let's drop them from struct platform_nand_ctrl. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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Boris Brezillon authored
None of the boards seem to overload the ->dev_ready() hook, just drop this field from orion_nand_data. Signed-off-by:
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Boris Brezillon authored
None of the existing drivers are overloading the ->scan_bbt() method, let's get rid of it and replace calls to ->scan_bbt() by nand_create_bbt() ones. Signed-off-by:
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Boris Brezillon authored
Rename nand_default_bbt() into nand_create_bbt() and pass it a nand_chip object to prepare removal of the chip->scan_bbt() hook. We add a temporary nand_default_bbt() wrapper which will be dropped after the removal of ->scan_bbt(). Signed-off-by:
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Boris Brezillon authored
struct device_node is defined in linux/of.h. Let's include this file instead of having a forward declaration of this struct. Signed-off-by:
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Boris Brezillon authored
struct mtd_info is defined in linux/mtd/mtd.h which is included at the beginning of nand_base.c, there's thus no need for the forward declaration of mtd_info. Signed-off-by:
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Boris Brezillon authored
nand_do_read() is a static function implemented in nand_base.c. There's no good reason to expose its prototype in rawnand.h. Signed-off-by:
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Boris Brezillon authored
Leaving a function pointer to NULL should be enough to trigger a NULL pointer exception, and anyway, if we want to BUG() when some missing hooks are called, this should be done in the core, so let's drop the cafe_nand_bug() dummy function. Signed-off-by:
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Boris Brezillon authored
This allows us to increase compile-test coverage without having to build a kernel for MIPS. That's particularly interesting for subsystem maintainers that want to test as many drivers as possible in a single build. We also add a dependency on HAS_IOMEM in BCMA_HOST_SOC to make sure the driver is not selected when the arch does not implement IO accessors. Signed-off-by:
Kalle Valo <kvalo@codeaurora.org> Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARCH_W90X900 enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARCH_QCOM enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARCH_MXC enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
asm/mach/flash.h does not seem to be needed, drop this #include to make the code completely machine and arch independent and allow one to compile it when COMPILE_TEST=y. Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARM, ARM64 or MIPS enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test these drivers without having ARCH_LPC32XX enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARCH_PXA enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
We don't need mach/hardware.h and sm/mach-types.h, and asm/io.h can be replaced by linux/io.h. Now that we removed those inclusions, we're ready to allow selection of this driver when COMPILE_TEST=y. Signed-off-by:
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Boris Brezillon authored
It just makes NAND maintainers' life easier by allowing them to compile-test this driver without having ARCH_OMAP2PLUS or ARCH_KEYSTONE enabled. We also need to add a dependency on HAS_IOMEM to make sure the driver compiles correctly. Signed-off-by:
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Boris Brezillon authored
When COMPILE_TEST is allowed and the platform needs uses the iomem API we need to add an explicit dependency on HAS_IOMEM to avoid selection of these drivers when building for an arch that has no iomem support (this is the case of arch/um). Signed-off-by:
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Boris Brezillon authored
The MTD_NAND_GPMI_NAND entry is already defined in an 'if MTD_NAND' block, no need to add an extra "depends on MTD_NAND". Signed-off-by:
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Abhishek Sahu authored
NAND parts can have bitflips in an erased page due to the process technology used. In this case, QCOM NAND controller is not able to identify that page as an erased page. Currently the driver calls nand_check_erased_ecc_chunk() for identifying the erased pages but this won’t work always since the checking is being with ECC engine returned data. In case of bitflips, the ECC engine tries to correct the data and then it generates the uncorrectable error. Now, this data is not equal to original raw data. For erased CW identification, the raw data should be read again from NAND device and this nand_check_erased_ecc_chunk function() should be called for raw data only. Now following logic is being added to identify the erased codeword bitflips. 1. In most of the cases, not all the codewords will have bitflips and only single CW will have bitflips. So, there is no need to read the complete raw page data. The NAND raw read can be scheduled for any CW in page. The NAND controller works on CW basis and it will update the status register after each CW read. Maintain the bitmask for the CW which generated the uncorrectable error. 2. Do raw read for all the CW's which generated the uncorrectable error. 3. Both DATA and OOB need to be checked for number of 0. The top-level API can be called with only data buf or OOB buf so use chip->databuf if data buf is null and chip->oob_poi if OOB buf is null for copying the raw bytes temporarily. 4. For each CW, check the number of 0 in cw_data and usable oob bytes, The bbm and spare (unused) bytes bit flip won’t affect the ECC so don’t check the number of bitflips in this area. Signed-off-by:
Abhishek Sahu <absahu@codeaurora.org> Signed-off-by:
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