- 27 May, 2020 2 commits
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Aric Cyr authored
[Why] If VUPDATE_END is before VUPDATE_START the delay calculated can become very large, causing a soft hang. [How] Take the absolute value of the difference between START and END. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Simon Ser authored
get_cursor_position already handles the case where the cursor has negative off-screen coordinates by not setting dc_cursor_position.enabled. Signed-off-by:
Simon Ser <contact@emersion.fr> Fixes: 626bf90f ("drm/amd/display: add basic atomic check for cursor plane") Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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- 26 May, 2020 1 commit
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Kevin Wang authored
the origin design will use varible of "attr->states" to save node supported states on current gpu device, but for multi gpu device, when probe second gpu device, the driver will check attribute node states from previous gpu device wthether to create attribute node. it will cause other gpu device create attribute node faild. 1. add member attr_list into amdgpu_device to link supported device attribute node. 2. add new structure "struct amdgpu_device_attr_entry{}" to track device attribute state. 3. drop member "states" from amdgpu_device_attr. v2: 1. move "attr_list" into amdgpu_pm and rename to "pm_attr_list". 2. refine create & remove device node functions parameter. fix: drm/amdgpu: optimize amdgpu device attribute code Signed-off-by:Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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- 22 May, 2020 7 commits
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Felix Kuehling authored
This fixes an intermittent bug where a root PD clear operation still in progress could overwrite a PDE update done by the CPU, resulting in a VM fault. Fixes: 108b4d92 ("drm/amd/amdgpu: Update VM function pointer") Reported-by:
Jay Cornwall <Jay.Cornwall@amd.com> Tested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] Previously we used the s3 codepath for gpu reset. This can lead to issues in certain case where we end of waiting for fences which will never come (because parts of the hw are off due to gpu reset) and we end up waiting forever causing a deadlock. [How] Handle GPU reset separately from normal s3 case. We essentially need to redo everything we do in s3, but avoid any drm calls. For GPU reset case suspend: -Acquire DC lock -Cache current dc_state -Commit 0 stream/planes to dc (this puts dc into a state where it can be powered off) -Disable interrupts resume -Edit cached state to force full update -Commit cached state from suspend -Build stream and plane updates from the cached state -Commit stream/plane updates -Enable interrupts -Release DC lock v2: -Formatting -Release dc_state Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Alex Deucher authored
Add some APU flags to simplify handling of different APU variants. It's easier to understand the special cases if we use names flags rather than checking device ids and silicon revisions. v2: rebase on latest code Acked-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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chen gong authored
[Problem description] 1. Boot up picasso platform, launches desktop, Don't do anything (APU enter into "gfxoff" state) 2. Remote login to platform using SSH, then type the command line: sudo su -c "echo manual > /sys/class/drm/card0/device/power_dpm_force_performance_level" sudo su -c "echo 2 > /sys/class/drm/card0/device/pp_dpm_sclk" (fix SCLK to 1400MHz) 3. Move the mouse around in Window 4. Phenomenon : The screen frozen Tester will switch sclk level during glmark2 run time. APU will enter "gfxoff" state intermittently during glmark2 run time. The system got hanged if fix GFXCLK to 1400MHz when APU is in "gfxoff" state. [Debug] 1. Fix SCLK to X MHz 1400: screen frozen, screen black, then OS will reboot. 1300: screen frozen. 1200: screen frozen, screen black. 1100: screen frozen, screen black, then OS will reboot. 1000: screen frozen, screen black. 900: screen frozen, screen black, then OS will reboot. 800: Situation Nomal, issue disappear. 700: Situation Nomal, issue disappear. 2. SBIOS setting: AMD CBS --> SMU Debug Options -->SMU Debug --> "GFX DLDO Psm Margin Control": 50 : Situation Nomal, issue disappear. 45 : Situation Nomal, issue disappear. 40 : Situation Nomal, issue disappear. 35 : Situation Nomal, issue disappear. 30 : screen black. 25 : screen frozen, then blurred screen. 20 : screen frozen. 15 : screen black. 10 : screen frozen. 5 : screen frozen, then blurred screen. 3. Disable GFXOFF feature Situation Nomal, issue disappear. [Why] Through a period of time debugging with Sys Eng team and SMU team, Sys Eng team said this is voltage/frequency marginal issue not a F/W or H/W bug. This experiment proves that default targetPsm [for f=1400MHz] is not sufficient when GFXOFF is enabled on Picasso. SMU team think it is an odd test conditions to force sclk="1400MHz" when GPU is in "gfxoff" state，then wake up the GFX. SCLK should be in the "lowest frequency" when gfxoff. [How] Disable gfxoff when setting manual mode. Enable gfxoff when setting other mode(exiting manual mode) again. By the way, from the user point of view, now that user switch to manual mode and force SCLK Frequency, he don't want SCLK be controlled by workload.It becomes meaningless to "switch to manual mode" if APU enter "gfxoff" due to lack of workload at this point. Tips: Same issue observed on Raven. Signed-off-by:
chen gong <curry.gong@amd.com> Reviewed-by:
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Alex Deucher authored
Fix typos that prevented them from showing up. v2: switch other files in addition to pp_clk_voltage Fixes: 4e01847c ("drm/amdgpu: optimize amdgpu device attribute code") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1150Signed-off-by:
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Alex Deucher authored
We need to get the silicon revision id before we parse the firmware in order to load the correct gpu info firmware for raven2 variants. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1103Acked-by:
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Alex Deucher authored
Move it into the fw_info function since it's logically part of the same functionality. Acked-by:
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- 21 May, 2020 30 commits
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Alan Swanson authored
Try to resize BAR0 to let CPU access all of VRAM on Navi. Syncs code with previous gfx generations from commit d6895ad3 ("drm/amdgpu: resize VRAM BAR for CPU access v6"). Signed-off-by:
Alan Swanson <reiver@improbability.net> Signed-off-by:
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Alex Deucher authored
It's not implemented yet so just drop it so the sysfs pcie bw file returns an appropriate error instead of garbage. Reviewed-by:
Yong Zhao <Yong.Zhao@amd.com> Reviewed-By:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Alex Deucher authored
1. Initialize the counters to 0 in case the callback fails to initialize them. 2. The counters don't exist on APUs so return an error for them. 3. Return an error if the callback doesn't exist. Reviewed-by:
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Philip Yang authored
In free memory of gpu path, remove bo from validate_list to make sure restore worker don't access the BO any more, then unregister bo MMU interval notifier. Otherwise, the restore worker will crash in the middle of validating BO user pages if MMU interval notifer is gone. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Dan Carpenter authored
This loop in the error handling code should start a "i - 1" and end at "i == 0". Currently it starts a "i" and ends at "i == 1". The result is that it removes one attribute that wasn't created yet, and leaks the zeroeth attribute. Fixes: 4e01847c ("drm/amdgpu: optimize amdgpu device attribute code") Acked-by:
Michael J. Ruhl <michael.j.ruhl@intel.com> Reviewed-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Gustavo A. R. Silva authored
The current codebase makes use of one-element arrays in the following form: struct something { int length; u8 data[1]; }; struct something *instance; instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL); instance->length = size; memcpy(instance->data, source, size); but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. So, replace the one-element array with a flexible-array member. Also, make use of the new struct_size() helper to properly calculate the size of struct smu10_voltage_dependency_table. This issue was found with the help of Coccinelle and, audited and fixed _manually_. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732 ("cxgb3/l2t: Fix undefined behaviour") Acked-by:Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by:
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Jinze Xu authored
[Why] When disconnect fe from be, something such as unstable clock may cause garbage occurs. [How] Send set avmute at the beginning of disable stream and send reset avmute at the end of enable stream. Signed-off-by:
Jinze Xu <jinze.xu@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
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Stylon Wang authored
[Why] When "max bpc" is set to enable deep color, some modes are removed from the list if they fail validation on max bpc. These modes should be kept if they validates fine with lower bpc. [How] - Retry with lower bpc in mode validation. - Same in atomic commit to apply working bpc, not necessarily max bpc. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Save the correct num vmid during resource creation and fix RN gpuvm level from 1 to 16 vmid entries. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] The minimum plane size we can support in DML is 16x16. If we try to pass a 16x16 plane with dynamic pipe split then validation will fail since it tries to split it into two pipes, each 8x8. Some userspace doesn't check that the commit fails and because the commit fails the old state is retained, resulting in corruption. [How] Add a workaround to avoid pipe split if any plane is 16x16 or smaller. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] We dropped the delay after changed the cursor functions locking the entire pipe to locking just the CURSOR registers to fix page flip stuttering - this introduced cursor stuttering instead, and an underflow issue. The cursor update can be delayed indefinitely if the cursor update repeatedly happens right around VUPDATE. The underflow issue can happen if we do a viewport update on a pipe on the same frame where a cursor update happens around VUPDATE - the old cursor registers are retained which can be in an invalid position. This can cause a pipe hang and indefinite underflow. [How] The complex, ideal solution to the problem would be a software triple buffering mechanism from the DM layer to program only one cursor update per frame just before VUPDATE. The simple workaround until we have that infrastructure in place is this change - bring back the delay until VUPDATE before locking, but with some corrections to the calculations. This didn't work for all timings before because the calculation for VUPDATE was wrong - it was using the offset from VSTARTUP instead and didn't correctly handle the case where VUPDATE could be in the back porch. Add a new hardware sequencer function to use the existing helper to calculate the real VUPDATE start and VUPDATE end - VUPDATE can last multiple lines after all. Change the udelay to incorporate the width of VUPDATE as well. Signed-off-by:
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Vladimir Stempen authored
[Why] DP training sequence to set SCRAMBLING_DISABLE bit properly based on training pattern - per DP Spec. [How] Update dpcd_pattern.v1_4.SCRAMBLING_DISABLE with 1 for TPS1, TPS2, TPS3, but not for TPS4. Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Rodrigo Siqueira authored
During the rework for removing the FPU issues, I found the following warning: [..] dml_common_defs.o: warning: objtool: dml_round()+0x9: FPU instruction outside of kernel_fpu_{begin,end}() This file has a single function that does not need to be in a specific file. This commit drop dml_common_defs file, and move dml_round function to dml_inline_defs. CC: Christian König <christian.koenig@amd.com> CC: Alexander Deucher <Alexander.Deucher@amd.com> CC: Peter Zijlstra <peterz@infradead.org> CC: Tony Cheng <tony.cheng@amd.com> CC: Harry Wentland <hwentlan@amd.com> Signed-off-by: -
Dmytro Laktyushkin authored
Current odm/mpc combine logic to detect which pipes need to split logically is flawed leading to incorrect pipe merge/split operations being taken. This change cleans up the logic and fixes the logical errors. Signed-off-by:
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Nikola Cornij authored
[why] Assigning a different DSC resource than the one previosly used is currently not handled. This causes black screen on mode change when more than one monitor is connected on some ASICs. [how] - Acquire the previously used DSC if available - Make sure re-program is triggered if new DSC is used Acked-by:
Nikola Cornij <nikola.cornij@amd.com> Signed-off-by:
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Likun Gao authored
Only ras supportted need to set MP1 state to prepare for unload before reloading SMU FW. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Evan Quan authored
Since the PCI bus number retrieved by PCI_BUS_NUM(pdev->devfn) is wrong. Signed-off-by:
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Jack Zhang authored
Under xgmi setup,some sysfs fail to create for the second time of kmd driver loading. It's due to sysfs nodes are not removed appropriately in the last unlod time. Changes of this patch: 1. remove sysfs for dev_attr_xgmi_error 2. remove sysfs_link adev->dev->kobj with target name. And it only needs to be removed once for a xgmi setup 3. remove sysfs_link hive->kobj with target name In amdgpu_xgmi_remove_device: 1. amdgpu_xgmi_sysfs_rem_dev_info needs to be run per device 2. amdgpu_xgmi_sysfs_destroy needs to be run on the last node of device. v2: initialize array with memset Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Evan Quan authored
The prompts will contain pci address(segment/bus/port/function), severity(warn or error) and some keywords(GPU, amdgpu). Also this address the issue that pci bus retrieved by PCI_BUS_NUM(adev->pdev->devfn) is wrong. Signed-off-by:
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Mario Kleiner authored
Testing on a Polaris11 gpu with DCE-11.2 suggests that it seems to work fine there, so optimistically enable it for DCE-11 and later. v2: drop DCE 11.0 hunk. Carrizo (DCE 11.0) has a HW bug where FP16 scaling doesn't work. The upscale and downscale factors were intended to block those FP16 cases and reject the commit but nobody ever added those to atomic check. Once those are added to atomic check, this can be re-enabled. Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by:
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Mario Kleiner authored
Expose support for DRM_FORMAT_ABGR16161616F and DRM_FORMAT_XBGR16161616F to the DRM core, complementing the already existing xRGB ordered fp16 formats. These are especially useful for creating presentable swapchains in Vulkan for VK_FORMAT_R16G16B16A16_SFLOAT. Signed-off-by:
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James Zhu authored
SCRATCH2 is used to keep decode wptr as a workaround which fix a hardware DPG decode wptr update bug for vcn2.5 beforehand. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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James Zhu authored
Remove JPEG_ENC_MASK from clock ungating since MJPEG encoder hasn't been support yet. Signed-off-by:
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John Clements authored
during ras recovery block smu access via smi Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Aishwarya Ramakrishnan authored
Return statements in functions returning bool should use true/false instead of 1/0. drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c:40:9-10: WARNING: return of 0/1 in function 'event_interrupt_isr_v9' with return type bool Generated by: scripts/coccinelle/misc/boolreturn.cocci Signed-off-by:
Aishwarya Ramakrishnan <aishwaryarj100@gmail.com> Signed-off-by:
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Harry Wentland authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Harry Wentland authored
[Why & How] One call was forcing stutter on instead of looking at the debug option. Ensure we always check the debug option unless we want to force stutter off. Signed-off-by:
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Harry Wentland authored
[Why] At bringup we want to be able to disable various power features. [How] These features are already exposed as dc_debug_options and exercised on other OSes. Create a new dc_debug_mask module parameter and expose relevant bits, in particular * DC_DISABLE_PIPE_SPLIT * DC_DISABLE_STUTTER * DC_DISABLE_DSC * DC_DISABLE_CLOCK_GATING Signed-off-by:
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Kevin Wang authored
the amdgpu device attribute node will be created accordding to sriov vf mode at runtime. cleanup unnecessary sriov check in attribute operation function. Signed-off-by:
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Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2020-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Fix for TypeC power domain toggling on resets (Cc: stable). Two compile time warning fixes. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200520123227.GA21104@jlahtine-desk.ger.corp.intel.com
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