Commits · 191a3c04799e4d1c1153442647629669bbf6c882 · Kirill Smelkov / linux · GitLab

27 Oct, 2020 40 commits

drm/amdgpu: enable MULTI_MON_PP_MCLK_SWITCH DC feature at default · 191a3c04

Evan Quan authored Sep 30, 2020

With this, for multiple monitors in sync(e.g. with the same model),
mclk switching will be allowed. That helps saving some idle power on
some ASICs(e.g. Polaris).
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

191a3c04

drm/amd/display: correct asic type check V2 · a2475e62

Evan Quan authored Sep 30, 2020

Check chip family also to avoid wrong identification.

V2: use the correct macro without AMDGPU prefix
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

a2475e62

drm/amd/pm: drop redundant display setting · b1878847

Evan Quan authored Sep 29, 2020

As this is already performed in smu7_set_power_state_tasks().
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b1878847

drm/amd/pm: reconfigure smc on display vbitimeout setting change · 62ff83a4

Evan Quan authored Sep 29, 2020

Reconfigure smc display settings on vbitimeout change.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

62ff83a4

drm/amd/pm: correct the mclk switching setting · d49873c9

Evan Quan authored Jun 18, 2020

Correct the mclk switching setting for multiple displays.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

d49873c9

drm/amd/pm: enable Polaris watermark table setting · b03fd3e7

Evan Quan authored Sep 28, 2020

Enable watermark table setting for Polaris.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b03fd3e7

drm/amd/pm: fulfill the Polaris implementation for get_clock_by_type_with_latency() · 690cdc26

Evan Quan authored Sep 28, 2020

Fulfill Polaris get_clock_by_type_with_latency().
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

690cdc26

drm/amd/pm: correct vddc_dep_on_dal_pwrl setup · db6f5c7f

Evan Quan authored Sep 25, 2020

Correct Polaris10 setup.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

db6f5c7f

drm/amd/pm: correct SMC sclk/mclk boot level setup · 9182fefc

Evan Quan authored Sep 25, 2020

Correct Polaris smc boot level setup.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

9182fefc

drm/amd/pm: correct pcie spc cap setup · 8f97e221

Evan Quan authored Sep 25, 2020

Correct Polaris10 pcie spc cap setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8f97e221

drm/amd/pm: correct clk/voltage dependence setup · ba4601fe

Evan Quan authored Sep 25, 2020

Correct Polaris10 clk/voltage dependence setup.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

ba4601fe

drm/amd/pm: correct the way to get the highest vddc · be56f22b

Evan Quan authored Sep 25, 2020

Populate the correct highest vddc setting on Polaris.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

be56f22b

drm/amd/pm: correct sclk/mclk dpm enablement · d765129a

Evan Quan authored Sep 25, 2020

Correct Polaris10 sclk/mclk dpm enablement.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

d765129a

drm/amd/pm: correct smc voltage controller setup · baa495f7

Evan Quan authored Sep 25, 2020

Correct Polaris10 smc voltage controller setup.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

baa495f7

drm/amd/pm: correct platformcaps setup · 326d0ff7

Evan Quan authored Sep 25, 2020

Correct Polaris10 platformcaps setup.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

326d0ff7

drm/amd/pm: correct VRconfig setting · 55411d16

Evan Quan authored Sep 25, 2020

Correct Polaris VRconfig setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

55411d16

drm/amd/pm: correct vddc phase control setting · a6d8a6eb

Evan Quan authored Sep 25, 2020

Correct Polaris10 vddc phase control.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

a6d8a6eb

drm/amd/pm: correct avfs fuse settings · b23dbd60

Evan Quan authored Sep 25, 2020

Correct Polaris10 avfs fuse setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

b23dbd60

drm/amd/pm: correct Polaris DIDT configurations · dba19531

Evan Quan authored Sep 25, 2020

Correct Polaris DIDT enablement.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

dba19531

drm/amd/pm: correct Polaris powertune table setup · d8b61d5a

Evan Quan authored Sep 25, 2020

Correct powertune table setup for Polaris.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

d8b61d5a

drm/amd/pm: correct the checks for sclk/mclk SS support · f6638d0e

Evan Quan authored Sep 25, 2020

Correct sclk/mclk SS support checks.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

f6638d0e

drm/amd/pm: correct VR shared rail info · a8588b8b

Evan Quan authored Sep 25, 2020

Add VR shared rail info.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

a8588b8b

drm/amd/pm: add mc register table initialization · 5f92b48c

Evan Quan authored Sep 25, 2020

Add mc register table initialization.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

5f92b48c

drm/amd/pm: add edc leakage controller setting · 8f0804c6

Evan Quan authored Sep 25, 2020

Enable edc controller table setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8f0804c6

drm/amd/pm: setup zero rpm parameters for polaris10 · 9610a3bf

Evan Quan authored Sep 11, 2020

Only if the ZeroRPM feature is supported.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

9610a3bf

drm/amd/pm: correct polaris10 clock stretcher data table setting · c420418f

Evan Quan authored Jun 18, 2020

By using the saved copy of ro_range_maximum and ro_range_minimum.
Correct the setting for "LdoRefSel".
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

c420418f

drm/amd/pm: correct the settings for ro range minimum and maximum · a90e6fbe

Evan Quan authored Sep 11, 2020

Make the settings more precise.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

a90e6fbe

drm/amd/pm: drop redundant efuse mask calculations · 029479ac

Evan Quan authored Sep 11, 2020

By moving that in atomfw_read_efuse().
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

029479ac

drm/amd/pm: optimize AC timing programming · 55544082

Evan Quan authored Jun 18, 2020

Programming AC Timing Parameters is only dependent on MCLK.
No need to nest loop for each SCLK DPM level.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

55544082

drm/amd/powerplay: separate Polaris fan table setup from Tonga · 18973c6e

Evan Quan authored Jun 18, 2020

Instead of sharing the fan table setup with Tonga, Polaris has
its own fan table setup.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

18973c6e

drm/amd/pm: add PWR_CKS_CNTL setting · 8c23cc29

Evan Quan authored Jun 18, 2020

This is for some special Polaris10 ASICs.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8c23cc29

drm/amdgpu: correct CG_ACLK_CNTL setting · 92995254

Evan Quan authored Jun 18, 2020

Correct polaris CG_ACLK_CNTL setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

92995254

drm/amd/pm: drop arb table first byte workaround · 7f95a2e0

Evan Quan authored Jun 18, 2020

As this is not needed for polaris.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

7f95a2e0

drm/amd/pm: add pptable VRHotLevel setting · e9016fc2

Evan Quan authored Jun 18, 2020

Add missing VRHotLevel setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

e9016fc2

drm/amd/pm: correct the BootLinkLevel setup · 3a9f6bb2

Evan Quan authored Jun 18, 2020

Set the BootLinkLevel as the max level.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3a9f6bb2

drm/amd/pm: correct the ACPI table setup V2 · a193d977

Evan Quan authored Jun 18, 2020

Correct the setting for "ActivityLevel".

V2: rich the comment
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

a193d977

drm/amd/pm: correct mclk table setup · 0232af1c

Evan Quan authored Jun 18, 2020

Correct the settings for "StutterEnable" and "EnabledForActivity".
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

0232af1c

drm/amd/pm: correct sclk table setup · 374b0781

Evan Quan authored Jun 18, 2020

Correct Polaris10 sclk table setup.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

374b0781

drm/amd/pm: correct vddci table setup · 8849fe64

Evan Quan authored Jun 18, 2020

Make sure the settings are applied only when voltage
controlled by gpio.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8849fe64

drm/amd/pm: populate smc samu table · 3df9931b

Evan Quan authored Jun 18, 2020

Add missing smc samu table setup.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3df9931b