- 30 Apr, 2016 1 commit
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Andrzej Hajda authored
clock_enable callback is used only by FIMD->DP pipeline. Similar but more universal functionality provides pipeline clock. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <daeinki@gmail.com>
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- 29 Apr, 2016 29 commits
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Andrzej Hajda authored
According to documentation HDMI-PHY must be on prior to MIXER configuration. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
According to documentation and tests HDMI-PHY must be on prior to MIXER configuration. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
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Andrzej Hajda authored
Components belonging to the same pipeline often requires synchronized clocks. Such clocks are sometimes provided by external clock controller, but they can be also provided by pipeline components. In latter case there should be a way to access them from another component belonging to the same pipeline. This is the case of: - DECON,FIMD -> HDMI and HDMI-PHY clock, - FIMD -> DP and DP clock in FIMD. The latter case has been solved by clock_enable callback in exynos_drm_crtc_ops. This solutin will not work with HDMI path as in this case clock is provided by encoder. This patch provides more generic solution allowing to register pipeline clock during initialization in exynos_drm_crtc structure. This way the clock will be easily accessible from both components. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
The helper abstracts out conversion from pipeline to crtc. Currently it is used in two places, but there will be more uses in next patches. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
decon_atomic_begin and decon_atomic_flush protects all windows already. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
Resetting IP at starting ensures that DECON will be in known state regardless of changes by bootloader. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
DECON should be updated after un-protecting windows and after changing output parameters, otherwise image is not displayed in case of HDMI path. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
HDMI registry dump unnecessary spoils console and is not very helpful. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
To ensure HDMI-PHY reprogramming will not affect HDMI the latter should be reset. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
HDMI-PHY power off bit defaults to 0 in older HDMI versions. In case of Exynos5433 it defaults to 1. To make code consistent across all versions this bit is always unset/set in power on/off sequences. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
Proper PHY configuration should be as follow: 1. set HDMI clock parents to OSCCLK. 2. reconfigure PHY. 3. set HDMI clock parents to PHY. 4. wait for PLL stabilization. The patch fixes it and consolidates the code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
DECON-TV(Display and Enhancement Controller for TV) is a variation of DECON IP. Its main purpose is to produce video stream for HDMI IP. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
DECON IP requires this clock to access configuration registers. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
HDMI on Exynos5433 differs from previous versions: - different HDMI-PHY settings, - different clocks, - SYSREG registers for enabling reference clock, - MODE_SET register in HDMI-PHY. It is distinguished from other variants by different compatible string. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
Exynos5433 variant of HDMI requires different set of clocks and sysreg phandle to system registers. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
There is no point in rewriting default values, as the IP is reset anyway. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
The patch performs following clean-ups: - remove unnecessary white spaces, - remove obvious comments, - fix tabulations, - remove NULL initializators, - re-order driver data. The patch does not change driver's behavior. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
HDMI-PHY configurations are stored as array pointer and count pair, we can re-use existing helpers to simplify their initialization. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
These variables should not be modified. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
With incoming support for newer SoCs different set of clocks will be required, depending on IP version. The patch prepares the driver for it. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Javier Martinez Canillas authored
Commit 254d4d11 ("drm/exynos: Add dependency for G2D in Kconfig") made the DRM_EXYNOS_G2D symbol to only be selectable if the s5p-g2d V4L2 driver is not enabled, since both use the same HW IP block. But added the dependency as depends on !VIDEO_SAMSUNG_S5P_G2D which isn't correct since Kconfig expressions are not boolean but tristate. So it will only evaluate to 'n' if VIDEO_SAMSUNG_S5P_G2D=y but it will evaluate to m if VIDEO_SAMSUNG_S5P_G2D=m. This means that both the V4L2 and DRM drivers can be enabled if the former is enabled as a module, which is not what we want. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Dan Carpenter authored
The "ret = regmap_write()" assignment was missing so this error message is never printed. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Dan Carpenter authored
We accidentally return success instead of a negative error code here. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Marek Szyprowski authored
Commit 1feafd3a ("drm/exynos: add exynos5420 support for fimd") add support for Exynos 5420 SoC, but it broke enabling display clock feature because of incorrect condition check. This patch fixes it, so display is working again on platforms requiring display clock control (i.e. Exynos5250-based SNOW platform). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
Fbdev code should be compiled only if CONFIG_DRM_FBDEV_EMULATION option is enabled. The patch fixes exynos-drm code trying to manipulate fbdev data which is not initialized in case CONFIG_DRM_FBDEV_EMULATION is disabled. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Andrzej Hajda authored
exynos_plane_mode_set should use adjusted_mode from the same atomic state as plane state. Otherwise it will result in incorrect behavior in case crtc mode changes. The patch fixes bug with black console framebuffer in case of command mode panels. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Arnd Bergmann authored
gcc-6 warns about a pointless loop in exynos_drm_subdrv_open: drivers/gpu/drm/exynos/exynos_drm_core.c: In function 'exynos_drm_subdrv_open': drivers/gpu/drm/exynos/exynos_drm_core.c:104:199: error: self-comparison always evaluates to false [-Werror=tautological-compare] list_for_each_entry_reverse(subdrv, &subdrv->list, list) { Here, the list_for_each_entry_reverse immediately terminates because the subdrv pointer is compared to itself as the loop end condition. If we were to take the current subdrv pointer as the start of the list (as we would do if list_for_each_entry_reverse() was not a macro), we would iterate backwards over the &exynos_drm_subdrv_list anchor, which would be even worse. Instead, we need to use list_for_each_entry_continue_reverse() to go back over each subdrv that was successfully opened until the first entry. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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http://git.agner.ch/git/linux-drm-fsl-dcuDave Airlie authored
This adds very rudimentary TCON (timing controller for raw LCD displays) support to enable the bypass mode in order to use the DCU controller on Freescale/NXP Vybrid SoC's. Additionally the register clock and pixel clock has been separated, but are currently still enabled and disabled pairwise. Other than that, fixes and cleanups accross the driver. * 'for-next' of http://git.agner.ch/git/linux-drm-fsl-dcu: drm/fsl-dcu: increment version and date drm/fsl-dcu: implement lastclose callback drm/fsl-dcu: disable output polling on driver unload drm/fsl-dcu: deallocate fbdev CMA on unload drm/fsl-dcu: use variable name dev for struct drm_device drm/fsl-dcu: handle missing panel gracefully drm/fsl-dcu: detach panel on destroy drm/layerscape: reduce excessive stack usage drm/fsl-dcu: add TCON driver drm/fsl-dcu: use common clock framework for pixel clock divider drm/fsl-dcu: add extra clock for pixel clock drm/fsl-dcu: disable clock on initialization failure and remove
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Dave Airlie authored
Merge tag 'sun4i-drm-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into drm-next Allwinner DRM driver for 4.7 This pull request introduces the sun4i driver, meant to be used on the older Allwinner SoCs (A10, A13, A20, A23, A31 and A33). It currently supports only the A13, which has one of the simplest video pipeline. Support for other video components and SoCs will be added eventually. It supports only a RGB or composite output. It doesn't do HDMI, VGA, LVDS or power management yet, but that will come in time as well. * tag 'sun4i-drm-for-4.7' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: MAINTAINERS: Add a maintainer for the Allwinner DRM driver drm: sun4i: tv: Add NTSC output standard drm: sun4i: tv: Add PAL output standard drm: sun4i: Add composite output drm: sun4i: Add RGB output drm: Add Allwinner A10 Display Engine support drm: sun4i: Add DT bindings documentation drm: fb: Add seq_file definition
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- 28 Apr, 2016 8 commits
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Maxime Ripard authored
Add myself as the maintainer of the new Allwinner DRM driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Add the settings to support the NTSC standard. Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Now that we have support for the composite output, we can start adding new supported standards. Start with PAL, and we will add other eventually. Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Some Allwinner SoCs have an IP called the TV encoder that is used to output composite and VGA signals. In such a case, we need to use the second TCON channel. Add support for that TV encoder. Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
One of the A10 display pipeline possible output is an RGB interface to drive LCD panels directly. This is done through the first channel of the TCON that will output our video signals directly. Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
The Allwinner A10 and subsequent SoCs share the same display pipeline, with variations in the number of controllers (1 or 2), or the presence or not of some output (HDMI, TV, VGA) or not. Add a driver with a limited set of features for now, and we will hopefully support all of them eventually Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
The display pipeline of the Allwinner A10 is involving several loosely coupled components. Add a documentation for the bindings. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Otherwise, building with DEBUG_FS enabled will trigger a build warning because we're using a structure that has not been declared. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- 26 Apr, 2016 2 commits
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Daniel Vetter authored
Need to move the free function around a bit, but otherwise mostly just removing code. Specifically we can nuke all the _locked variants since the weak idr reference is now protected by the idr_mutex, which we never hold anywhere expect in the lookup/reg/unreg functions. And those never call anything else. Another benefit of this is that this patch switches the weak reference logic from kref_put_mutex to kref_get_unless_zero. And the later is in general more flexible wrt accomodating multiple weak references protected by different locks, which might or might not come handy eventually. But one consequence of that switch is that we need to acquire the blob_lock from the free function for the list_del calls. That's a bit tricky to pull off, but works well if we pick the exact same scheme as is already used for framebuffers. Most important changes: - filp list is maintainer by create/destroy_blob ioctls directly (already the case, so we can just remove the redundant list_del from the free function). - filp close handler walks the filp-private list lockless - works because we know no one else can access it. I copied the same comment from the fb code over to explain this. - Otherwise we need to sufficiently restrict blob_lock critical sections to avoid all the unreference calls. Easy to do once the blob_lock only protects the list, and no longer the weak reference. Cc: Dave Airlie <airlied@gmail.com> Cc: Daniel Stone <daniels@collabora.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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Daniel Vetter authored
Random drive-by refactoring I spotted. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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