- 15 Apr, 2019 40 commits
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Adrian Hunter authored
In preparation for removing finish_tasklet, call mmc_request_done() from the IRQ handler if possible. That will alleviate the potential loss of performance from shifting away from finish_tasklet. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Reviewed-by:
Faiz Abbas <faiz_abbas@ti.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
In preparation for removing finish_tasklet, move some processing from sdhci_request_done() to __sdhci_finish_mrq(). Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Reviewed-by:
Faiz Abbas <faiz_abbas@ti.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
In preparation for removing finish_tasklet, move some functions. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Reviewed-by:
Faiz Abbas <faiz_abbas@ti.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Adrian Hunter authored
In preparation for removing finish_tasklet, reorganize sdhci_finish_mrq() and __sdhci_finish_mrq() to separate the tasklet scheduling from other processing. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Reviewed-by:
Faiz Abbas <faiz_abbas@ti.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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YueHaibing authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/memstick/host/jmb38x_ms.c: In function 'jmb38x_ms_issue_cmd': drivers/memstick/host/jmb38x_ms.c:371:17: warning: variable 'data' set but not used [-Wunused-but-set-variable] It's never used since introduction and can be removed. Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ulf Hansson authored
Cc: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Acked-by:
Chaotian Jing <chaotian.jing@mediatek.com>
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Adrian Hunter authored
Add PCI Ids for Intel CML. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Andrea Merello authored
pwrseq_emmc.c implements a HW reset procedure for eMMC chip by driving a GPIO line. It registers the .reset() cb on mmc_pwrseq_ops and it registers a system restart notification handler; both of them perform reset by unconditionally calling gpiod_set_value(). If the eMMC reset line is tied to a GPIO controller whose driver can sleep (i.e. I2C GPIO controller), then the kernel would spit warnings when trying to reset the eMMC chip by means of .reset() mmc_pwrseq_ops cb (that is exactly what I'm seeing during boot). Furthermore, on system reset we would gets to the system restart notification handler with disabled interrupts - local_irq_disable() is called in machine_restart() at least on ARM/ARM64 - and we would be in trouble when the GPIO driver tries to sleep (which indeed doesn't happen here, likely because in my case the machine specific code doesn't call do_kernel_restart(), I guess..). This patch fixes the .reset() cb to make use of gpiod_set_value_cansleep(), so that the eMMC gets reset on boot without complaints, while, since there isn't that much we can do, we avoid register the restart handler if the GPIO controller has a sleepy driver (and we spit a dev_notice() message to let people know).. This had been tested on a downstream 4.9 kernel with backported commit 83f37ee7ba33 ("mmc: pwrseq: Add reset callback to the struct mmc_pwrseq_ops") and commit ae60fb031cf2 ("mmc: core: Don't do eMMC HW reset when resuming the eMMC card"), because I couldn't boot my board otherwise. Maybe worth to RFT. Signed-off-by:
Andrea Merello <andrea.merello@gmail.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Fabien Parent authored
'top_base' memory region is optional. Check that the resource is valid before using it. This avoid getting a "invalid resource" error message printed by the kernel. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Daniel Drake authored
DMA on this hardware is limited to dealing with a single page at a time. Previously, the driver was set up accordingly to request single-page DMA buffers, however that had the effect of generating a large number of small MMC requests for data I/O. Improve the driver to accept scatter-gather DMA buffers of larger sizes. Iterate through those buffers a page at a time. Testing with dd, this increases write performance from 2mb/sec to 10mb/sec, and increases read performance from 4mb/sec to 14mb/sec. Signed-off-by:
Daniel Drake <drake@endlessm.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Faiz Abbas authored
According to the AM654x Data Manual[1], the setup timing in lower speed modes can only be met if the controller uses a falling edge data launch. To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25 speed modes. Use the sdhci writeb callback to implement this condition. [1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1 Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ulf Hansson authored
The amount of changes to the memorystick subsystem are limited as of today. However, I have a couple of times been funneling changes through my MMC tree and it have turned out fine. So, I am here by volunteering to continue doing this, by adding myself and the link to the MMC tree to the MEMSTICK section. Cc: Alex Dubov <oakad@yahoo.com> Cc: Alex Dubov <alex.dubov@gmail.com> Cc: Maxim Levitsky <maximlevitsky@gmail.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com> Cc: Rui Feng <rui_feng@realsil.com.cn> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Acked-by:
Maxim Levitsky <maximlevitsky@gmail.com>
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Ulf Hansson authored
The current SONY MEMORYSTICK CARD SUPPORT section is pointing to the TI flash media memorystick driver, which is a bit confusing. Let's make this more clear by moving this part into TI FLASH MEDIA INTERFACE DRIVER section, but rename the section to TI FLASH MEDIA MEMORYSTICK/MMC DRIVERS, as to make it more clear. Finally, add Alex Dubov to the SONY MEMORYSTICK STANDARD SUPPORT, as I believe that has been the intention. Cc: Alex Dubov <oakad@yahoo.com> Cc: Alex Dubov <alex.dubov@gmail.com> Cc: Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Andy Shevchenko authored
Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Andy Shevchenko authored
- spaces surrounding arithmetic operators - utilize full line limit - drop extra spaces / TABs in variable definitions Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Andy Shevchenko authored
For easy grepping on debug purposes join string literals back in the messages. No functional change. While here, join list of module authors as well. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Andy Shevchenko authored
The mmc pointer can't be NULL at ->remove(), drop the useless check. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Andy Shevchenko authored
Driver core sets it to NULL upon probe failure or release. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ludovic Barre authored
This patch allows to get datactrl configuration specific at variant. This introduce more flexibility on datactlr value. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ludovic Barre authored
This patch defines get_dctrl_cfg callback for sdmmc variant. sdmmc variant has specific stm32 transfer modes. sdmmc data transfer mode selection could be: -Block data transfer ending on block count. -SDIO multibyte data transfer. -MMC Stream data transfer (not used). -Block data transfer ending with STOP_TRANSMISSION command. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ludovic Barre authored
This patch defines get_dctrl_cfg callback for qcom variant. qcom variant has a specific block size definition. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ludovic Barre authored
This patch defines get_dctrl_cfg callback for legacy variants whatever DMA_ENGINE configuration. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> [Ulf: Fixed a build error] Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ludovic Barre authored
This patch adds get_datactrl_cfg callback in mmci_host_ops to allow to get datactrl configuration specific at variant. Common helper function is defined and could be call by variant. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Daniel Drake authored
Enable the DMA codepath for writes as well as reads. This improves write speed from 1mb/sec to 2mb/sec (tested with dd). The original ampe_stor vendor driver also uses DMA for writes. Signed-off-by:
Daniel Drake <drake@endlessm.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Christoph Muellner authored
Direct commands (DCMDs) are an optional feature of eMMC 5.1's command queue engine (CQE). The Arasan eMMC 5.1 controller uses the CQHCI, which exposes a control register bit to enable the feature. The current implementation sets this bit unconditionally. This patch allows to suppress the feature activation, by specifying the property disable-cqe-dcmd. Signed-off-by:
Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by:
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Fixes: 84362d79 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: stable@vger.kernel.org Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Christoph Muellner authored
Add disable-cqe-dcmd as optional property for MMC hosts. This property allows to disable or not enable the direct command features of the command queue engine. Signed-off-by:
Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by:
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Fixes: 84362d79 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1") Cc: stable@vger.kernel.org Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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YueHaibing authored
Fix sparse warning: drivers/mmc/host/sdhci-omap.c:788:6: warning: symbol 'sdhci_omap_reset' was not declared. Should it be static? Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
Faiz Abbas <faiz_abbas@ti.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
Tegra CQHCI/SDHCI design prevents write access to SDHCI block size register when CQE is enabled and unhalted. CQHCI driver enables CQE prior to invoking sdhci_cqe_enable which violates this Tegra specific host requirement. This patch fixes this by configuring sdhci block registers prior to CQE unhalt. This patch also has a fix for retry of unhalt due to known Tegra specific CQE resume bug where first unhalt might not succeed when clear all tasks is performed prior to resume and need a second unhalt. This patch also includes CQE enable fix for CMD CRC errors that happen with the specific sandisk emmc device when status command is sent during the transfer of last data block due to marginal timing. Tested-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
This patch adds define for CBC field mask of the register CQHCI_SSC1. Tested-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
Tegra186 CQHCI host has a known bug where CQHCI controller selects DATA_PRESENT_SELECT bit to 1 for DCMDs with R1B response type and since DCMD does not trigger any data transfer, DCMD task complete happens leaving the DATA FSM of host controller in wait state for the data. This effects the data transfer tasks issued after the DCMDs with R1b response type resulting in timeout. SW WAR is to set CMD_TIMING to 1 in DCMD task descriptor. This bug and SW WAR is applicable only for Tegra186 and not for Tegra194. This patch implements this WAR thru NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING for Tegra186 and also implements update_dcmd_desc of cqhci_host_ops interface to set CMD_TIMING bit depending on the NVQUIRK. Tested-by:
Jon Hunter <jonathanh@nvidia.com> Reviewed-by:
Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
This patch adds update_dcmd_desc interface to cqhci_host_ops to allow hosts to update any of the DCMD task descriptor attributes and parameters. Tested-by:
Jon Hunter <jonathanh@nvidia.com> Reviewed-by:
Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
SDHCI controller of Tegra194 is similar to SDHCI controller in Tegra186. This patch documents Tegra194 sdhci compatible string. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
This patch includes below HW tuning related fixes. configures tuning parameters as per Tegra TRM WAR fix for manual tap change HW auto-tuning post process As per Tegra TRM, SDR50 mode tuning execution takes upto maximum of 256 tuning iterations and SDR104/HS200/HS400 modes tuning execution takes upto maximum of 128 tuning iterations. This patch programs tuning control register with maximum tuning iterations needed based on the timing along with the start tap, multiplier, and step size used by the HW tuning. Tegra210 has a known issue of glitch on trimmer output when the tap value is changed with the trimmer input clock running and the WAR is to disable card clock before sending tuning command and after sending tuning command wait for 1usec and issue SW reset followed by enabling card clock. This WAR is applicable when changing tap value manually as well. Tegra SDHCI driver has this implemented correctly for manual tap change but missing SW reset before enabling card clock during sending tuning command. Issuing SW reset during tuning command as a part of WAR and is applicable in cases where tuning is performed with single step size for more iterations. This patch includes this fix. HW auto-tuning finds the best largest passing window and sets the tap at the middle of the window. With some devices like sandisk eMMC driving fast edges and due to high tap to tap delay in the Tegra chipset, auto-tuning does not detect falling tap between the valid windows resulting in a parital window or a merged window and the best tap is set at the signal transition which is actually the worst tap location. Recommended SW solution is to detect if the best passing window picked by the HW tuning is a partial or a merged window based on min and max tap delays found from chip characterization across PVT and perform tuning correction to pick the best tap. This patch has implementation of this post HW tuning process for the tegra hosts that support HW tuning through the callback function tegra_sdhci_execute_hw_tuning and uses the tuned tap delay. Tested-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
As per the Host Controller Standard Specification Version 4.20, limitation of tuning iteration count is removed as PLL locking time can be longer than UHS-1 tuning due to larger PVT fluctuation and it will result in increase of tuning iteration to complete the tuning. This patch creates sdhci_host member tuning_loop_count to allow hosts to specify maximum tuning iterations and also updates execute_tuning to use this specified maximum tuning iteration count. Default tuning_loop_count is set to same as existing loop count of MAX_TUNING_LOOP which is 40 iterations. Tested-by:
Jon Hunter <jonathanh@nvidia.com> Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
ddr_signaling is set to true for DDR50 and DDR52 modes but is not set back to false for other modes. This programs incorrect host clock when mode change happens from DDR52/DDR50 to other SDR or HS modes like incase of mmc_retune where it switches from HS400 to HS DDR and then from HS DDR to HS mode and then to HS200. This patch fixes the ddr_signaling to set properly for non DDR modes. Tested-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Cc: stable@vger.kernel.org # v4.20 + Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Fabien Parent authored
Add the MSDC configuration for the MT8516 SoC. Signed-off-by:
Fabien Parent <fparent@baylibre.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Wolfram Sang authored
The CBSY flag should be proper before calling tmio_mmc_host_probe() because this function will already use write16 which checks this bit. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Wolfram Sang authored
max_req_size is calculated by 'max_blk_size * max_blk_count' in the TMIO core. So, specifying U32_MAX as max_blk_count will overflow this calculation. It will cause no harm in practice because the immense high number will overflow into another immense high number. However, it is not good coding practice, so calculate max_blk_count so that max_req_size will fit into unsigned int on ARM32/64. Thanks to the Renesas BSP team for the bug report! Reported-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Wolfram Sang authored
We will need it later for other calculations. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Wolfram Sang authored
Mostly year updates, but one addition as well. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Niklas Söderlund <niklas.soderlund@ragnatech.se> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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