- 18 Dec, 2018 16 commits
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Geert Uytterhoeven authored
The Port F Control Register 3 (PFCR3) contains only a single field. However, counting from left to right, it is the fourth field, not the first field. Insert the missing dummy configuration values (3 fields of 16 values) to fix this. The descriptor for the Port F Control Register 0 (PFCR0) lacks the description for the 4th field (PF0 Mode, PF0MD[2:0]). Add the missing configuration values to fix this. Fixes: a8d42fc4 ("sh-pfc: Add sh7264 pinmux support") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
While the SEL_PWM[0-3] fields in the Module Select Register 0 support 4 possible configurations per PWM pin, only the first 3 are valid. Replace the invalid and unused configurations for SEL_PWM[0-3]_3 by dummies. Fixes: 794a6711 ("pinctrl: sh-pfc: Initial R8A77995 PFC support") Signed-off-by:
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Geert Uytterhoeven authored
The SEL_I2C1 (MOD_SEL0[21:20]) field in Module Select Register 0 has a width of 2 bits, i.e. it allows programming one out of 4 different configurations. However, the MOD_SEL0_21_20 macro contains 8 values instead of 4, overflowing into the subsequent fields in the register, and thus breaking the configuration of the latter. Fix this by dropping the bogus last 4 values, including the non-existent SEL_I2C1_4 configuration. Fixes: 6d4036a1 ("pinctrl: sh-pfc: Initial R8A77990 PFC support") Signed-off-by:
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Geert Uytterhoeven authored
The Peripheral Function Select Register 11 contains 3 reserved bits and 15 variable-width fields, but the variable field descriptor does not contain the 3-bit field IP11[25:23]. Fixes: 856cb4bb ("sh: Add support pinmux for SH7734") Signed-off-by:
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Geert Uytterhoeven authored
The Module Select Register 0 contains 20 (= 5 x 4) reserved bits, and 12 single-bit fields, but the variable field descriptor lacks a field of 4 reserved bits. Fixes: f5912524 ("pinctrl: sh-pfc: Add R8A77980 PFC support") Signed-off-by:
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Geert Uytterhoeven authored
The Module Select Register 0 contains 20 (= 5 x 4) reserved bits, and 12 single-bit fields, but the variable field descriptor lacks a field of 4 reserved bits. Fixes: b92ac66a ("pinctrl: sh-pfc: Add R8A77970 PFC support") Signed-off-by:
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Geert Uytterhoeven authored
The Peripheral Function Select Register 9 contains 12 fields, but the variable field descriptor contains a 13th bogus field of 3 bits. Fixes: 43c4436e ("pinctrl: sh-pfc: add R8A7794 PFC support") Signed-off-by:
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Geert Uytterhoeven authored
Add a build-time check, to ensure the number of pins and pin marks in a pin group matches. This helps catching bugs early. Signed-off-by:
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Geert Uytterhoeven authored
The tpu4_to3_mux[] array contains the TPU4TO3 pin mark, but the tpu4_to3_pins[] array lacks the corresponding pin number. Add the missing pin number, for non-GPIO pin F26. Fixes: 5da4eb04 ("sh-pfc: sh73a0: Add TPU pin groups and functions") Signed-off-by:
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Geert Uytterhoeven authored
The vin1_b_data18_mux[] arrays contains pin marks for the 2 LSB bits of the color components. The vin1_b_data18_pins[] array rightfully does not include the corresponding pin numbers, as RGB18 is subset of RGB24, containing only the 6 MSB bits of each component. Fixes: 8e32c967 ("pinctrl: sh-pfc: r8a7791: Add VIN pins") Signed-off-by:
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Geert Uytterhoeven authored
The qspi_data4_b_mux[] array contains pin marks for the clock and chip select pins. The qspi_data4_b_pins[] array rightfully does not contain the corresponding pin numbers, as the control pins are provided by a separate group (qspi_ctrl_b). Fixes: 2d0c386f ("pinctrl: sh-pfc: r8a7791: Add QSPI pin groups") Signed-off-by:
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Geert Uytterhoeven authored
The lcd0_data24_1_pins[] array contains the LCD0 D1[2-5] pin numbers, but the lcd0_data24_1_mux[] array lacks the corresponding pin marks. Fixes: 06c7dd86 ("sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions") Signed-off-by:
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Geert Uytterhoeven authored
The gether_gmii_mux[] array contains the REF125CK pin mark, but the gether_gmii_pins[] array lacks the corresponding pin number. Fixes: bae11d30 ("sh-pfc: r8a7740: Add GETHER pin groups and functions") Signed-off-by:
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Geert Uytterhoeven authored
Due to an interaction with commit 9f2b76a2 ("pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC support"), the state of the I/O Control Registers is saved/restored during s2ram on RZ/G2E, but not on R-Car E3. Hence on R-Car E3, SDHI voltage state is lost after system resume. Fix this by registering the I/O Control Registers on R-Car E3, too. Fixes: 33847a71 ("pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI") Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
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Nicholas Mc Guire authored
devm_kasprintf() may return NULL on failure of internal allocation thus the assignments are not safe if not checked. On error rza1_pinctrl_register() respectively rza1_parse_gpiochip() return negative values so -ENOMEM in the (unlikely) failure case of devm_kasprintf() should be fine here. Signed-off-by:
Nicholas Mc Guire <hofrat@osadl.org> Fixes: 5a49b644 ("pinctrl: Renesas RZ/A1 pin and gpio controller") Signed-off-by:
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Geert Uytterhoeven authored
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) states that the USB30_OVC pin supports pull-up only. It has a bit assigned in the pull-enable register (PUEN5), but not in the pull-up/down control register (PUD5). Add a check for this, to prevent configuring a prohibited setting. Reported-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Fixes: 83f6941a ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by:
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- 04 Dec, 2018 2 commits
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Phil Edworthy authored
If we assign the result of of_get_child_count() to an unsigned int, the code will not detect any errors. Therefore assign it to an int instead. Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
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Phil Edworthy authored
This fixes the check for unused mdio bus setting and the following static checker warning: drivers/pinctrl/pinctrl-rzn1.c:198 rzn1_pinctrl_mdio_select() warn: always true condition '(ipctl->mdio_func[mdio] >= 0) => (0-u32max >= 0)' Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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- 23 Nov, 2018 2 commits
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Chris Brandt authored
Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs. Signed-off-by:
Chris Brandt <chris.brandt@renesas.com> Reviewed-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by:
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Chris Brandt authored
Add device tree binding documentation and header file for Renesas R7S9210 (RZ/A2) SoCs. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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- 20 Nov, 2018 1 commit
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Dmitry Shifrin authored
Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by:Dmitry Shifrin <dmitry.shifrin@cogentembedded.com> Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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- 19 Nov, 2018 10 commits
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Takeshi Kihara authored
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by:Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> [geert: Move canfd from common to automotive] Signed-off-by:
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Takeshi Kihara authored
This patch adds CAN{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds CAN{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: -
Takeshi Kihara authored
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by:Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by:
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Takeshi Kihara authored
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 ES1.x SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: -
Takeshi Kihara authored
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: -
Ulrich Hecht authored
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs. Signed-off-by:
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Geert Uytterhoeven authored
The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and will conflict with generic macros that are to be added. Signed-off-by:
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Takeshi Kihara authored
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77990 SoC. Signed-off-by:Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by:
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- 13 Nov, 2018 9 commits
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Jacopo Mondi authored
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3. Signed-off-by:
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Jacopo Mondi authored
The VIN4 and VIN5 interfaces support parallel video input. Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car M3-N. Signed-off-by:
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Jacopo Mondi authored
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car M3-W R8A7796 SoC. Fixes: a5c2949f ("pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitions") Signed-off-by:
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Jacopo Mondi authored
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car H3 R8A7795 SoC. Fixes: 9942a5b5 ("pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitions") Signed-off-by:
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Jacopo Mondi authored
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car V2H R8A7792 SoC. Fixes: 7dd74bb1 ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups") Signed-off-by:
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Jacopo Mondi authored
VIN data groups may appear on different sets of pins, usually named "vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support appending the '_a' or '_b' suffix, leading to the definition of group names not consistent with the ones defined using the SH_PFC_PIN_GROUP() macro. Fix this by making the VIN_DATA_PIN_GROUP macro a variadic one, which accepts an optional 'version' argument. Fixes: 423caa52 ("pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header file") Signed-off-by:
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Dmitry Shifrin authored
Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: -
Takeshi Kihara authored
This patch supports the {get,set}_io_voltage operations of SDHI. This operates the IOCTRL30 register on the R8A77990 SoC and makes 1.8V/3.3V signal voltage switch possible. Signed-off-by: -
Takeshi Kihara authored
This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by:
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