1. 26 Apr, 2016 2 commits
    • Peter Swain's avatar
      i2c: octeon: Improve performance if interrupt is early · 1bb1ff3e
      Peter Swain authored
      There is a race between the TWSI interrupt and the condition
      that is required before proceeding:
      
      Low-level: interrupt flag bit must be set
      High-level controller: valid bit must be clear
      
      If the interrupt comes too early and the condition is not met
      the wait will time out, and the transfer is aborted leading
      to very poor performance.
      
      To avoid this race retry for the condition ~80 µs later.
      The retry is avoided on the very first invocation of
      wait_event_timeout() (which tests the condition before entering
      the wait and is therefore always wrong in this case).
      
      EEPROM reads on 100kHz i2c now measure ~5.2kB/s, about 1/2 what's
      achievable, and much better than the worst-case 100 bytes/sec before.
      
      While at it remove the debug print from the low-level wait function.
      Signed-off-by: default avatarPeter Swain <pswain@cavium.com>
      Signed-off-by: default avatarJan Glauber <jglauber@cavium.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      1bb1ff3e
    • Jan Glauber's avatar
      i2c: octeon: Remove zero-length message support · 392d01de
      Jan Glauber authored
      Zero-length message support (SMBUS QUICK or i2c) never worked with
      the Octeon hardware. Disable SMBUS QUICK support and bail out in
      case of a zero-length i2c request.
      
      After this change 'i2c-detect -q' will return an error on Octeon but
      the previously reported results were wrong anyway.
      Signed-off-by: default avatarJan Glauber <jglauber@cavium.com>
      Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
      392d01de
  2. 25 Apr, 2016 10 commits
  3. 24 Apr, 2016 5 commits
  4. 22 Apr, 2016 15 commits
  5. 16 Apr, 2016 2 commits
  6. 14 Apr, 2016 4 commits
  7. 13 Apr, 2016 2 commits