Skip to content

L
linux
Switch branch/tag
  1. 03 Feb, 2023 5 commits
  3. 02 Feb, 2023 9 commits
  5. 01 Feb, 2023 18 commits
  7. 31 Jan, 2023 8 commits
    • Mark Brown's avatar
      ASoC: cs42l42: Add SoundWire support · 98fda42a
      Mark Brown authored 
      Merge series from Stefan Binding <sbinding@opensource.cirrus.com>:

The CS42L42 has a SoundWire interface for control and audio. This
chain of patches adds support for this.

Patches #1 .. #5 split out various changes to the existing code that
are needed for adding Soundwire. These are mostly around clocking and
supporting the separate probe and enumeration stages in SoundWire.

Patches #6 .. #8 actually adds the SoundWire handling.
      98fda42a
    • Mark Brown's avatar
      ASoC: use helper function and cleanup · 6570befb
      Mark Brown authored 
      Merge series from Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>:

struct snd_soc_dai need to have info for playback/capture,
but it is using "playback/capture_xxx" or "tx/tx_xxx" or array.
This kind of random definition is very difficult to read.

This patch-set add helper functions and each driver use it.
And cleanup the definition.
      6570befb
    • Mark Brown's avatar
      ASoC: mchp-spdifrx: add runtime PM support and fixes · 01b17067
      Mark Brown authored 
      Merge series from Claudiu Beznea <claudiu.beznea@microchip.com>:

This series adds runtime PM support for Microchip SPDIFRX driver.
Along with it I added few fixes identified while going though the code
and playing with Microchip SPDIFRX controller.
      01b17067
    • Mark Brown's avatar
      ASoC: codecs: Add Awinic AW88395 audio amplifier · 41e0207f
      Mark Brown authored 
      Merge series from wangweidong.a@awinic.com:

The Awinic AW88395 is an I2S/TDM input, high efficiency
digital Smart K audio amplifier with an integrated 10.25V
smart boost converter.

Add a DT schema for describing Awinic AW88395 audio amplifiers. They are
controlled using I2C
      41e0207f
    • Mark Brown's avatar
      Add the Renesas IDT821034 codec support · 381ee169
      Mark Brown authored 
      Merge series from Herve Codina <herve.codina@bootlin.com>:

The Renesas IDT821034 codec is four channel PCM codec with on-chip
filters and programmable gain setting.  It also provides SLIC
(Subscriber Line Interface Circuit) signals as GPIOs.
      381ee169
    • Stefan Binding's avatar
      ASoC: cs42l42: Wait for debounce interval after resume · 16838bfb
      Stefan Binding authored 
      Since clock stop causes bus reset on Intel controllers, we need
to wait for the debounce interval on resume, to ensure all the
interrupt status registers are set correctly.
Signed-off-by: default avatarStefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-9-sbinding@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      16838bfb
    • Richard Fitzgerald's avatar
      ASoC: cs42l42: Don't set idle_bias_on · e0bd53a4
      Richard Fitzgerald authored 
      idle_bias_on was set because cs42l42 has a "VMID" type pseudo-midrail
supply (named FILT+), and these typically take a long time to charge.
But the driver never enabled pm_runtime so it would never have powered-
down the cs42l42 anyway.

In fact, FILT+ can charge to operating voltage within 12.5 milliseconds
of enabling HP or ADC. This time is already covered by the startup
delay of the HP/ADC.

The datasheet warning about FILT+ taking up to 1 second to charge only
applies in the special cases that either the PLL is started or
DETECT_MODE set to non-zero while both HP and ADC are off. The driver
never does either of these.

Removing idle_bias_on allows the Soundwire host controller to suspend
if there isn't a snd_soc_jack handler registered.
Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: default avatarStefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-8-sbinding@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      e0bd53a4
    • Richard Fitzgerald's avatar
      ASoC: cs42l42: Add SoundWire support · 90f6a2a2
      Richard Fitzgerald authored 
      This adds support for using CS42L42 as a SoundWire device.

SoundWire-specifics are kept separate from the I2S implementation as
much as possible, aiming to limit the risk of breaking the I2C+I2S
support.

There are some important differences in the silicon behaviour between
I2S and SoundWire mode that are reflected in the implementation:

- ASP (I2S) most not be used in SoundWire mode because the two interfaces
  share pins.

- The SoundWire capture (record) port only supports 1 channel. It does
  not have left-to-right duplication like the ASP.

- DP2 can only be prepared if the HP has powered-up. DP1 can only be
  prepared if the ADC has powered-up. (This ordering restriction does
  not exist for ASPs.) The SoundWire core port-prepare step is
  triggered by the DAI-link prepare(). This happens before the
  codec DAI prepare() or the DAPM sequence so these cannot be used
  to enable HP/ADC. Instead the HP/ADC enable/disable are done during
  the port_prep callback.

- The SRCs are an integral part of the audio chain but in silicon their
  power control is linked to the ASP. There is no equivalent power link
  to SoundWire DPs so the driver must take "manual" control of SRC power.

- The SoundWire control registers occupy the lower part of the SoundWire
  address space so cs42l42 registers are offset by 0x8000 (non-paged) in
  SoundWire mode.

- Register addresses are 8-bit paged in I2C mode but 16-bit unpaged in
  SoundWire.

- Special procedures are needed on register read/writes to (a) ensure
  that the previous internal bus transaction has completed, and
  (b) handle delayed read results, when the read value could not be
  returned within the SoundWire read command.

There are also some differences in driver implementation between I2S
and SoundWire operation:

- CS42L42 I2S does not runtime_suspend, but runtime_suspend/resume support
  has been added into the driver in SoundWire mode as the most convenient
  way to power-up the bus manager and to handle the unattach_request
  condition, though the CS42L42 chip does not itself suspend or resume.

- Intel SoundWire host controllers have a low-power clock-stop mode that
  requires resetting all peripherals when resuming. This means that the
  interrupt registers will be reset in between the interrupt being
  generated and the interrupt being handled, and since the interrupt
  status is debounced, these values may not be accurate immediately,
  and may cause spurious unplug events before settling.

- As in I2S mode, the PLL is only used while audio is active because
  of clocking quirks in the silicon. For SoundWire the cs42l42_pll_config()
  is deferred until the DAI prepare(), to allow the cs42l42_bus_config()
  callback to set the SCLK.
Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: default avatarStefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-7-sbinding@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      90f6a2a2
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7