- 28 Oct, 2021 40 commits
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Michael Strauss authored
[WHY] On certain configs, SMU clock table voltages don't match which cause parser to behave incorrectly by leaving dcfclk and socclk table entries unpopulated. [HOW] Currently the function that finds the corresponding clock for a given voltage only checks for exact voltage level matches. In the case that no match gets found, parser now falls back to searching for the max clock which meets the requested voltage (i.e. its corresponding voltage is below requested). Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Qingqing Zhuo authored
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN301 to DML, where all FPU code should locate. Cc: Christian König <christian.koenig@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
Zhan Liu <Zhan.Liu@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Qingqing Zhuo <Qingqing.Zhuo@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] We have a regression that cause maximize lane settings to use uninitialized data from unused lanes. This will cause link training to fail for 1 or 2 lanes because the lane adjust is populated incorrectly sometimes. v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex) Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Wenjing Liu <wenjing.liu@amd.com> Signed-off-by:
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Wenjing Liu authored
[why] option 1: disallow different lanes to have different lane settings option 2: dpcd lane settings will always use the same hw lane settings even if it doesn't match requested lane adjust Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Wenjing Liu authored
[why] As DP features expands, we have encountered many situations where we must configure a different DPCD lane setting from hw lane settings we output. The change is to decouple hw lane settings from dpcd lane settings to provide flexibility to configure dpcd and hw individually. Reviewed-by:
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Wenjing Liu authored
[why] Decouple lane settings decision logic all to its own function. The function takes in lane adjust array and link training settings and decide what hw lane setting and dpcd lane setting should be used. Reviewed-by:
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Wenjing Liu authored
[how] revision 8 SCR requires DP Source to write TPS2 and FFE lane adjustment in one 5 byte write aux transaction. It specifies to read aux rd interval value as soon as we turn on TPS1 pattern. Cc: Wayne Lin <wayne.lin@amd.com> Acked-by:
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Meenakshikumar Somasundaram authored
[Why] To fix the check condition for fec enable for dpia links in MST mode. [How] dc_link_should_enable_fec() to be used to check whether fec should be enabled in MST mode. Cc: Wayne Lin <wayne.lin@amd.com> Reviewed-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Acked-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by:
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Meenakshikumar Somasundaram authored
[Why] To fix the check condition for fec enable for dpia links. [How] dc_link_should_enable_fec() to be used to check whether fec should be enabled. Cc: Wayne Lin <wayne.lin@amd.com> Reviewed-by:
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Jimmy Kizito authored
[Why] Certain docks appear to NAK I2C writes to the segment pointer with the MOT (middle of transaction) bit clear. This behaviour can cause EDID reads from higher segments to fail. [How] Add workaround flag for links which connect to docks exhibiting this issue. Cc: Wayne Lin <wayne.lin@amd.com> Reviewed-by:
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Hansen authored
[Why] B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or PHYC/PHY D. [How] Based on chip internal hardware revision id determine it is B0 and set DMUB scratch register so DMUBFW can connect the display pipe is connected correctly to the dig. Cc: Wayne Lin <wayne.lin@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Hansen <Hansen.Dsouza@amd.com> Signed-off-by:
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Martin Leung authored
why: DCN303's 4 channel SOC BB causes problems at strobe how: workaround to manually adjust strobe calculation using FCLK restrict. Reviewed-by:
Agustin Gutierrez <agustin.gutierrez@amd.com> Tested-by:
Martin Leung <Martin.Leung@amd.com> Signed-off-by:
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Aric Cyr authored
This new DC version brings improvements in the following areas: - Improvements for USB4; - Isolate FPU code for DCN20, DCN301, and DSC; - Fixes on Linking training; - Refactoring some parts of the code, such as PSR; Acked-by:
Aric Cyr <aric.cyr@amd.com> Signed-off-by:
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Anthony Koo authored
Acked-by:
Anthony Koo <Anthony.Koo@amd.com> Signed-off-by:
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Anson Jacob authored
fixed16_to_double & fixed16_to_double_to_cpu are not used. Reviewed-by:
Anson Jacob <Anson.Jacob@amd.com> Signed-off-by:
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Dmytro Laktyushkin authored
This change adds a config flag to allow non fullscreen MPO during ODM. Scaling calculation will still fail configurations where video is only one one side of the screen. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
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Guo, Bing authored
Why: For audio packet type 0x02, there are 2 Layouts: Layout = 0 for 2 channels and Layout = 1 for > 2 channels. Layout will affect bandwidth check. Currently, for HDMI FRL, Layout field isn't set and has a default value of 0, so theoretically only 2-channel audio for audio packet type 0x02 is supported now. How: 1. Set Layout properly according to maximum audio channel numbers for audios with audio packet type 0x02. 2. 8ch LPCM audio is not supported for timing modes with v_active <= 576. Reviewed-by:
Chris Park <chris.park@amd.com> Tested-by:
Bing Guo <Bing.Guo@amd.com> Signed-off-by:
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Aric Cyr authored
We found a compilation error that we thought was caused by the 3DLUT patch; later on, we figured out the root cause of the problem, but we already applied the revert in the wrong patch. This commit brings it back the 3DLUT fix. Acked-by:
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Aric Cyr authored
Acked-by:
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Anthony Koo authored
- Add flag to control root clock gating in init_hw - Add flag to indicate a diags environment is being used Acked-by:
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Aric Cyr authored
[Why] When writing long AUX commands some sinks will respond will write status update requiring source to read status. [How] When a write request is replied with data (AUX_ACK_M), retry a read of write status to determine when the write is completed. Reviewed-by:
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George Shen authored
[Why] Currently the naming of preferred_training_settings is ambiguous and has caused confusion regarding its purpose and usage. [How] Add comment to clarify the intention. Reviewed-by:
George Shen <george.shen@amd.com> Signed-off-by:
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George Shen authored
[Why] Currently there are use cases that require DP link to maintain fixed VS and PE in HW regardless of what the sink requests. BIOS integrated info table will specify whether we need to use the fixed drive settings, and the drive settings to use. [How] Implement changes to parse the integrated info table and set the fixed drive settings accordingly. Reviewed-by:
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Dmytro Laktyushkin authored
Style change for better consistency across codebase Reviewed-by:
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Dmytro Laktyushkin authored
This is unnecessary in clk_mgr Reviewed-by:
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Michael Strauss authored
[WHY] Every other CM LUT power down sequence is deferred to next vupdate as memory powerdown updates immediately while selecting LUTs is double buffered. Previous update to defer LUT power down missed GAMCOR and DSCL, causing some visible flicker when entering/exiting fullscreen video playback. [HOW] Update dpp deferred update loop to check for valid DPPs in res_pool instead of referencing dcn_ip which turns out to not be populated during runtime. Move GAMCOR and DSCL powerdown to dpp deferred updates. Reviewed-by:
Haonan Wang <Haonan.Wang2@amd.com> Tested-by:
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Michael Strauss authored
[WHY] i2c memory doesn't get set to light sleep on hw init as intended [HOW] Set i2c to light sleep after reg gets zeroed, ensuring memory power control doesn't get disabled for any other DIO memory Reviewed-by:
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Ahmad Othman authored
[Why] Crash when USB4 is connected. [How] Added an ASIC specific code guard. Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Reviewed-by:
Ahmad Othman <Ahmad.Othman@amd.com> Signed-off-by:
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Qingqing Zhuo authored
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DSC to DML, where all FPU code should locate. This change does not refactor any functions but move code around. Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Ahmad Othman authored
[Why] Created new fields that matches new B0 structs On DCN31 the mapping of DIO output to PHY differs from A0 to B0 boards with new PHY C20 & this new mapping needed to be handled. [How] Mapped new structure based on new structs Added logic for mapping over A0 and B0 boards Hooked all new structs together. Reviewed-by:
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Robin Chen authored
[Why] To expose new power optimization flags to PSR interface. It allows the PSR related power features can be enabled separately base on different use scenarios. Reviewed-by:
Robin Chen <po-tchen@amd.com> Signed-off-by:
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Guo, Bing authored
Updating certain variable blanking calculations to use ceiling function. Reviewed-by:
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Anson Jacob authored
Limit when FPU is enabled to only functions that does FPU operations for dcn20_resource_construct, which gets called during driver initialization. Enabling FPU operation disables preemption. Sleeping functions(mutex (un)lock, memory allocation using GFP_KERNEL, etc.) should not be called when preemption is disabled. Fixes the following case caught by enabling CONFIG_DEBUG_ATOMIC_SLEEP in kernel config [ 1.338434] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:281 [ 1.347395] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 197, name: systemd-udevd [ 1.356356] CPU: 7 PID: 197 Comm: systemd-udevd Not tainted 5.13.0+ #3 [ 1.356358] Hardware name: System manufacturer System Product Name/PRIME X570-PRO, BIOS 3405 02/01/2021 [ 1.356360] Call Trace: [ 1.356361] dump_stack+0x6b/0x86 [ 1.356366] ___might_sleep.cold+0x87/0x98 [ 1.356370] __might_sleep+0x4b/0x80 [ 1.356372] mutex_lock+0x21/0x50 [ 1.356376] smu_get_uclk_dpm_states+0x3f/0x80 [amdgpu] [ 1.356538] pp_nv_get_uclk_dpm_states+0x35/0x50 [amdgpu] [ 1.356711] init_soc_bounding_box+0xf9/0x210 [amdgpu] [ 1.356892] ? create_object+0x20d/0x340 [ 1.356897] ? dcn20_resource_construct+0x46f/0xd30 [amdgpu] [ 1.357077] dcn20_resource_construct+0x4b1/0xd30 [amdgpu] ... Tested on: 5700XT (NAVI10 0x1002:0x731F 0x1DA2:0xE410 0xC1) Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Reviewed-by:
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Lewis Huang authored
[Why] When the vbios config and driver config are different, if we update clock to lower before call program_timing and program_pixel_clk, garbage appear. [How] Align bw context with hw config when system resume Reviewed-by:
Lewis Huang <Lewis.Huang@amd.com> Signed-off-by:
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Alex Deucher authored
For asics without a callback, use the current level rather than 0xff. This can avoid an unnecesary forced level set on older asics when set by the user. Reviewed-by:
Kevin Wang <kevinyang.wang@amd.com> Signed-off-by:
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Alex Deucher authored
Stutter mode is a power saving feature on GPUs, however at least one early raven system exhibits stability issues with it. Add a quirk to disable it for that system. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=214417 Fixes: 00544006 ("drm/amdgpu: enable gfxoff again on raven series (v2)") Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Tao Zhou authored
Remove GPRs init for ALDEBARAN in gpu reset temporarily, will add the init once the algorithm is stable. v2: Only remove GPRs init in gpu reset. v3: Suspend needs it, only skip it in gpu reset. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lang Yu authored
Actually, cu_mask has been copied to mqd memory and does't have to persist in queue_properties. Remove it from queue_properties. And use struct mqd_update_info to store such properties, then pass it to update queue operation. v2: * Rename pqm_update_queue to pqm_update_queue_properties. * Rename struct queue_update_info to struct mqd_update_info. * Rename pqm_set_cu_mask to pqm_update_mqd. Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Lang Yu <lang.yu@amd.com> Reviewed-by:
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Lang Yu authored
Currently, queue is updated with data in queue_properties. And all allocated resource in queue_properties will not be freed until the queue is destroyed. But some properties(e.g., cu mask) bring some memory management headaches(e.g., memory leak) and make code complex. Actually they have been copied to mqd and don't have to persist in queue_properties. Add an argument into update queue to pass such properties, then we can remove them from queue_properties. v2: Don't use void *. Suggested-by:
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Tao Zhou authored
Skip GPRs init in specific condition since current GPRs init algorithm only works for some CU settings. Signed-off-by:
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