- 09 Feb, 2021 10 commits
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Dom Cobley authored
Now that our HDMI controller supports CEC for the BCM2711, let's remove that flag. Reviewed-by:
Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by:
Dom Cobley <popcornmix@gmail.com> Signed-off-by:
Maxime Ripard <maxime@cerno.tech> Acked-by:
Hans Verkuil <hverkuil-cisco@xs4all.nl> Tested-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Maxime Ripard authored
The HDMI controller found in the BCM2711 has an external interrupt controller for the CEC and hotplug interrupt shared between the two instances. Let's add a variant flag to register a single interrupt handler and deals with the interrupt handler setup, or two interrupt handlers relying on an external irqchip. Signed-off-by:
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Maxime Ripard authored
The BCM2711 has two different interrupt sources to transmit and receive CEC messages, provided through an external interrupt chip shared between the two HDMI interrupt controllers. The rest of the CEC controller is identical though so we need to change a bit the code organisation to share the code as much as possible, yet still allowing to register independent handlers. Signed-off-by:
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Maxime Ripard authored
While the BCM2835 had the CEC clock derived from the HSM clock, the BCM2711 has a dedicated parent clock for it. Let's introduce a separate clock for it so that we can handle both cases. Reviewed-by:
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Maxime Ripard authored
As part of the enable sequence we might change the HSM clock rate if the pixel rate is different than the one we were already dealing with. On the BCM2835 however, the CEC clock derives from the HSM clock so any rate change will need to be reflected in the CEC clock divider to output 40kHz. Fixes: cd4cb49d ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate") Reviewed-by:
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Maxime Ripard authored
The CEC clock divider needs to output a frequency of 40kHz from the HSM rate on the BCM2835. The driver used to have a fixed frequency for it, but that changed for the BCM2711 and we now need to compute it dynamically to maintain the proper rate. Fixes: cd4cb49d ("drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate") Reviewed-by:
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Dom Cobley authored
Currently we call cec_phys_addr_invalidate on a hotplug deassert. That may be due to a TV power cycling, or an AVR being switched on (and switching edid). This makes CEC unusable since our controller wouldn't have a physical address anymore. Set it back up again on the hotplug assert. Fixes: 15b4511a ("drm/vc4: add HDMI CEC support") Signed-off-by:
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Dom Cobley authored
The commit 311e305f ("drm/vc4: hdmi: Implement a register layout abstraction") forgot one CEC register, and made a copy and paste mistake for another one. Fix those mistakes. Fixes: 311e305f ("drm/vc4: hdmi: Implement a register layout abstraction") Reviewed-by:
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Dom Cobley authored
The code prior to 311e305f ("drm/vc4: hdmi: Implement a register layout abstraction") was relying on the fact that the register offset was incremented by 4 for each readl call. That worked since the register width is 4 bytes. However, since that commit the HDMI_READ macro is now taking an enum, and the offset doesn't increment by 4 but 1 now. Divide the index by 4 to fix this. Fixes: 311e305f ("drm/vc4: hdmi: Implement a register layout abstraction") Reviewed-by:
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Dom Cobley authored
The hdmi reset got moved to a later point in the commit 9045e91a ("drm/vc4: hdmi: Add reset callback"). However, the reset now occurs after vc4_hdmi_cec_init and so tramples the setup of registers like HDMI_CEC_CNTRL_1 This only affects pi0-3 as on pi4 the cec registers are in a separate block Fixes: 9045e91a ("drm/vc4: hdmi: Add reset callback") Reviewed-by:
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- 04 Feb, 2021 25 commits
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Arnd Bergmann authored
After all users of the 'dm' warnings got hidden in an #ifdef, the compiler started warning about it being unused: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5380:33: error: unused variable 'dm' [-Werror,-Wunused-variable] Add another such #ifdef. Fixes: 98ab5f35 ("drm/amd/display: Fix deadlock during gpu reset v3") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125124849.102037-1-arnd@kernel.org
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Dave Airlie authored
Merge tag 'amd-drm-next-5.12-2021-02-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.12-2021-02-03: amdgpu: - Display fixes and cleanups - Vangogh fixes - Fix possible race when there are timeouts on two rings - SR-IOV fixes - Add missing license - DCE 10/12 bpc fixes - Display MALL fixes - Fix SMU user preference settings persistence - Fix retry in gem allocate - Add new PCI DID - Fix for manual fan speed control on cards where it was problematic - Fix regression in pinning GTT - Misc display fixes - Misc code cleanups amdkfd: - Fix config handling - Fix regression in buffer free From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210204045717.3823-1-alexander.deucher@amd.comSigned-off-by:
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Dave Airlie authored
Merge tag 'mediatek-drm-next-5.12' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.12 1. Decouple Mediatek DRM sub driver 2. Share mtk mutex driver for both DRM and MDP 3. Add support for SoC MT8183 Signed-off-by:
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Yongqiang Niu authored
Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by:
Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by:
Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by:
CK Hu <ck.hu@mediatek.com> Signed-off-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org>
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Yongqiang Niu authored
Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by:
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Yongqiang Niu authored
ccorr ctm matrix bits will be different in mt8192. Signed-off-by:
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Yongqiang Niu authored
Enable dither function to improve the display quality. Signed-off-by:
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Yongqiang Niu authored
Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled. Signed-off-by:
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Yongqiang Niu authored
1. Add ovl private data 2. Add rdma private data 3. Add gamma privte data 4. Add main and external path module for crtc create Signed-off-by:
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Yongqiang Niu authored
Not all SoC has dither function in gamma module. Add private data to control this function setting. Signed-off-by:
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Yongqiang Niu authored
mt8183 gamma module will different with mt8173, so separate gamma for adding private data. Signed-off-by:
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Hsin-Yi Wang authored
Current implementation of mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But other devices with different dev data would also call this function. Separate necessary parameters out so other device components (dither, gamma) can call this function. Signed-off-by:
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CK Hu authored
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, so move it to soc folder. Signed-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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CK Hu authored
Moving mutex resource management from client driver to mutex driver could prevent client drivers negotiating for resource management. Signed-off-by:
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CK Hu authored
mtk mutex is used by both drm and mdp driver, so change disp/ddp term to mutex to show that it's a common driver for drm and mdp. Signed-off-by:
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CK Hu authored
After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c has only mtk mutex function, so rename it to match the function in it. Signed-off-by:
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CK Hu authored
Those file includings are useless, so remove them. Signed-off-by:
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Yongqiang Niu authored
Get the fifo size from device tree because each rdma in the same SoC may have different fifo size Signed-off-by:
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Yongqiang Niu authored
The orginal setting is not correct, fix it to follow hardware data sheet. If keep this error setting, mt8173/mt8183 display ok but mt8192 display abnormal. Fixes: 0664d139 ("drm/mediatek: Add AAL engine basic function") Signed-off-by:
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Yongqiang Niu authored
add description for postmask postmask is used control round corner for display frame Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Hsin-Yi Wang authored
Similar to commit a9d9fea7 ("drm/mediatek: mtk_dsi: Create connector for bridges"): Use the drm_bridge_connector helper to create a connector for pipelines that use drm_bridge. This allows splitting connector operations across multiple bridges when necessary, instead of having the last bridge in the chain creating the connector and handling all connector operations internally. Signed-off-by:
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Yongqiang Niu authored
rdma fifo size may be different even in same SOC, add this property to the corresponding rdma Signed-off-by:
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Yongqiang Niu authored
It's possible that state->base.fb is null. Add a check before access its format. Fixes: b6b1bb98 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha") Signed-off-by:
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git://anongit.freedesktop.org/drm/drm-intelDave Airlie authored
- WARN if plane src coords are too big (Ville) - Prevent double YUV range correction on HDR planes (Andres) - DP MST related Fixes (Sean, Imre) - More clean-up around DRAM detection code (Jose) - Actually async flips enable for all ilk+ platforms (Ville) Signed-off-by:
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ssh://git.freedesktop.org/git/tegra/linuxDave Airlie authored
drm/tegra: Changes for v5.12-rc1 Adds support for newer firmware image versions of the Video Image Composer (VIC) and adds a comment clarifying the use of the STREAMID registers. Fixes a couple of issues with display and gr2d on older Tegra SoCs such as Tegra114, as well as a runtime PM reference leak. Signed-off-by:
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- 02 Feb, 2021 5 commits
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Dan Carpenter authored
If the user passes a "level" value which is higher than 31 then that leads to shift wrapping. The undefined behavior will lead to a syzkaller stack dump. Fixes: 5632708f ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Bernard Zhao authored
Remove unneeded variable: "pattern". Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Jinzhou Su authored
Check GFX DPM and PG bit before enable GFXOFF on Vangogh smu post init. Signed-off-by:
Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Better handling of dummy p-state table - Workaround for some legacy DP-VGA dongles - Add Freesync HDMI support to DMCU - Enable "trigger_hotplug" debugfs on all outputs - fix initial bounding box values for dcn3.02 - implement support for DID2.0 dsc passthrough - fix calculation for the pwl backlight curve - Fix multiple memory leaks Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Anson Jacob <Anson.Jacob@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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