- 20 Mar, 2020 40 commits
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Sandeep Maheswaram authored
Add support for overriding QUSB2 V2 phy tuning parameters in device tree bindings. Signed-off-by:
Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by:
Rob Herring <robh@kernel.org> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Reviewed-by:
Matthias Kaehlcke <mka@chromium.org> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com>
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Sandeep Maheswaram authored
Add generic QUSB2 V2 PHY table so the respective phys can use the same table. Signed-off-by:
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Sandeep Maheswaram authored
Add compatibles for generic QUSB2 V2 phy which can be used for sdm845 and sc7180. Signed-off-by:
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Sandeep Maheswaram authored
Convert QUSB2 phy bindings to DT schema format using json-schema. Signed-off-by:
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Christoph Muellner authored
phy-rockchip-inno-usb2 logs the message "phy-ff2c0000.syscon:usb2-phy@100.2: charger = INVALID_CHARGER" constantly with a frequency of about 1 Hz and a verbosity level of INFO. As this is clearly annoying, this patch decreases the log level to DEBUG. Signed-off-by:
Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by:
Heiko Stuebner <heiko@sntech.de> Signed-off-by:
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Hanjie Lin authored
This adds support for the USB2 PHY found in the Amlogic A1 SoC Family. It supports host mode only. Signed-off-by:
Yue Wang <yue.wang@amlogic.com> Signed-off-by:
Hanjie Lin <hanjie.lin@amlogic.com> Reviewed-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Hanjie Lin authored
Add the Amlogic A1 Family USB2 PHY Bindings It supports Host mode only. Signed-off-by:
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Grygorii Strashko authored
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding support for TI AM654x/J721E SoCs PHY interface selection. Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
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Grygorii Strashko authored
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding compatible strings to enable support for TI AM654x/J721E SoCs. Signed-off-by:
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Jorge Ramirez-Ortiz authored
Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the 20nm and 28nm process nodes. Based on Sriharsha Allenki's <sallenki@codeaurora.org> original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by:Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: Sriharsha Allenki's <sallenki@codeaurora.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Tested-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Jorge Ramirez-Ortiz authored
Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY appears in a number of SoCs on various flavors of 20nm and 28nm nodes. This commit adds information related to the 28nm node only. Based on Sriharsha Allenki's <sallenki@codeaurora.org> original definitions. [bod: converted to yaml format] Signed-off-by:
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Shawn Guo authored
Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. The PHY can come in two flavours femtoPHY or picoPHY. This commit adds support for the femtoPHY with the possibility of extending to the picoPHY with additional future commits. Both PHYs are on a 28 nanometer process node. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and from driver name Extended commit log to mention femtoPHY and picoPHY for future reference.] Signed-off-by:Shawn Guo <shawn.guo@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by:
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Sriharsha Allenki authored
Adds bindings for Qualcomm's 28 nm USB PHY supporting Low-Speed, Full-Speed and Hi-Speed USB connectivity on Qualcomm chipsets. [bod: Converted to YAML. Changed name dropping snps, 28nm components] Signed-off-by:
Sriharsha Allenki <sallenki@codeaurora.org> Signed-off-by:
Anu Ramanathan <anur@codeaurora.org> Signed-off-by:
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Jorge Ramirez-Ortiz authored
This binding is not used by any driver. Signed-off-by:
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Chunfeng Yun authored
Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by:
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Chunfeng Yun authored
The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it, this can avoid confusion when support new platforms Signed-off-by:
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Chunfeng Yun authored
Sometimes the reference clock of USB3 PHY comes from oscillator directly, and no need refer to a fixed-clock in DTS anymore if make it optional. Signed-off-by:
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Chunfeng Yun authored
This is used to tune J-K voltage by internal R (resistance), the range is [0, 31], the resistance value is about 6.9K ohm for 0, 3.8K ohm for 31, and the step is 1K ohm Signed-off-by:
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Chunfeng Yun authored
This is used to tune the threshold of disconnect, the index range is [0, 15], the threshold voltage is about 400mV for 0, 700mV for 15, and the step is 20mV. Signed-off-by:
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Chunfeng Yun authored
Add three required properties about the address mapping, including '#address-cells', '#size-cells' and 'ranges' Signed-off-by:
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Chunfeng Yun authored
Usually the digital and analog phys use the same reference clock, but on some platforms, they are separated, so add another optional clock to support it. In order to keep the clock names consistent with PHY IP's, use the da_ref for analog phy and ref clock for digital phy. Signed-off-by:
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Chunfeng Yun authored
The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it to avoid confusion Signed-off-by:
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Chunfeng Yun authored
Make the ref clock optional, then we no need refer to a fixed-clock in DTS anymore when the clock of USB3 PHY comes from oscillator directly Signed-off-by:
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Chunfeng Yun authored
Add two optional properties, one for tuning J-K voltage by INTR, another for disconnect threshold, both of them are related with connect detection Signed-off-by:
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Joe Perches authored
Arguments are supposed to be ordered high then low. Signed-off-by:
Joe Perches <joe@perches.com> Reviewed-by:
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Bjorn Andersson authored
The PCIe PHY initialization requires the attached device to be present, which is primarily achieved by the PCI controller driver. So move the logic from init/exit to power_on/power_off. Signed-off-by:
John Stultz <john.stultz@linaro.org> Reviewed-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Kunihiko Hayashi authored
Since this phy is shared by multiple devices including USB and PCIe, it is necessary to determine which device use this phy. This patch adds SoC-dependent functions to determine a device using this phy. When there is 'socionext,syscon' property in the pcie-phy node, the driver calls SoC-dependt function instead of checking .has_syscon in SoC-dependent data. The function configures the system controller to use phy for PCIe. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by:
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Kunihiko Hayashi authored
Add legacy SoC support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. This supports Pro5. This specifies only 1 port use because Pro5 doesn't set it in the power-on sequence. Signed-off-by:
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Kunihiko Hayashi authored
In case of using default parameters, communication failure might occur in rare cases. This sets Rx sync mode parameter to avoid the issue. Signed-off-by:
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Kunihiko Hayashi authored
Add legacy SoC support that needs to manage gio clock and reset. This supports Pro5. Signed-off-by:
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Kunihiko Hayashi authored
Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is equivalent to Pro4. Signed-off-by:
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Kunihiko Hayashi authored
This adds compatible string for Pro5 SoC that needs to manage gio clock and reset. And Pro4 SoC uses USB2 PHY instead of USB3 HS-PHY, so this removes Pro4 description from usb3-hsphy. Signed-off-by:
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Kunihiko Hayashi authored
Use devm_platform_ioremap_resource() to simplify the code. Signed-off-by:
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Bjorn Andersson authored
The support for the 14nm MSM8996 UFS PHY is currently handled by the UFS-specific 14nm QMP driver, due to the earlier need for additional operations beyond the standard PHY API. Add support for this PHY to the common QMP driver, to allow us to remove the old driver. Acked-by:
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Swapnil Jakhade authored
Implement single link subnode support to the phy driver. Add reset support including PHY reset and individual lane reset. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by:
Yuti Amonkar <yamonkar@cadence.com> Signed-off-by:
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Swapnil Jakhade authored
Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Signed-off-by:
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Swapnil Jakhade authored
Use regmap to read and write DPTX specific PHY registers. Signed-off-by:
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Swapnil Jakhade authored
Use regmap for accessing Torrent PHY registers. Modify register offsets as defined in Torrent PHY user guide. Abstract address calculation using regmap APIs. Signed-off-by:
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Swapnil Jakhade authored
Add support for PHY configuration APIs. These will mainly reconfigure link rate, number of lanes, voltage swing and pre-emphasis values. Signed-off-by:
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Swapnil Jakhade authored
Add configuration functions for 19.2 MHz refclock support. Add register configurations for SSC support. Signed-off-by:
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