Merge tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock changes from Chen-Yu Tsai:

 * Added support for fixed post-divider on divider and NKM-style clocks
 * Added driver for R40 CCU
 * Fix sunxi-ng/ccu-sunxi-r.h header file guard macro typo
 * Make fractional clock modes really used and correctly configured
 * Make H3 cpu clock rate change correctly to be used with cpufreq

* tag 'sunxi-clk-for-4.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: support R40 SoC
  dt-bindings: add compatible string for Allwinner R40 CCU
  clk: sunxi-ng: nkm: add support for fixed post-divider
  clk: sunxi-ng: div: Add support for fixed post-divider
  dt-bindings: clock: sunxi-ccu: Add compatibles for sun5i CCU driver
  clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
  clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
  clk: sunxi-ng: Wait for lock when using fractional mode
  clk: sunxi-ng: Make fractional helper less chatty
  clk: sunxi-ng: multiplier: Fix fractional mode
  clk: sunxi-ng: Fix fractional mode for N-M clocks
  clk: sunxi-ng: Fix header guard of ccu-sun8i-r.h

Merge tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

Changes in definitions of audio related clocks for Exynos5420/5422/5800
SoCs: a fix of mau_epll clock definition and changes enabling clock rate
setting propagation on a path from the I2S IP block up the EPLL.

* tag 'clk-v4.14-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: exynos542x: Enable clock rate propagation up to the EPLL
  clk: samsung: Add CLK_SET_RATE_PARENT to some AUDSS CLK CON clocks
  clk: samsung: Fix mau_epll clock definition for exynos5422

Pull Amlogic clock driver updates from Neil Armstrong:

 * meson8b: add the reset controller to the clkc
 * meson: expose all clk ids
 * gxbb-aoclk: Add CEC 32k clock
 * gxbb: add mmc input 0 clocks
 * meson: fix protection against undefined clks
 * gxbb: fix audio divider flags

* tag 'meson-clk-for-4.14' of git://github.com/baylibre/clk-meson:
  clk: meson: gxbb-aoclk: Add CEC 32k clock
  clk: meson: gxbb-aoclk: Switch to regmap for register access
  dt-bindings: clock: amlogic, gxbb-aoclkc: Update bindings
  clk: meson: gxbb: Add sd_emmc clk0 clocks
  clk: meson: gxbb: fix clk_mclk_i958 divider flags
  clk: meson: gxbb: fix meson cts_amclk divider flags
  clk: meson: meson8b: register the built-in reset controller
  dt-bindings: clock: gxbb-aoclk: Add CEC 32k clock
  clk: meson: gxbb: Add sd_emmc clk0 clkids
  clk: meson-gxbb: expose almost every clock in the bindings
  clk: meson8b: expose every clock in the bindings
  clk: meson: gxbb: fix protection against undefined clks
  clk: meson: meson8b: fix protection against undefined clks
  dt-bindings: clock: meson8b: describe the embedded reset controller

Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.

Add a compatible string for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

SATA PLL on Allwinner R40 is of type (parent) * N * K / M / 6 where 6 is
the fixed post-divider.

Add post-divider support for NKM type clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[wens@csie.org: Fixed application of post-divider in set_rate callback]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

The bindings were not updated when the sun5i CCU driver was added in
commit 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver").
Signed-off-by: Jonathan Liu <net147@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

The CLK_SET_RATE_PARENT flag is added to clocks between the EPLL
and the audio subsystem clock controller so that the EPLL's output
frequency can be set indirectly with clk_set_rate() on a leaf clock.
That should be safe as EPLL is normally only used to generate clock
for the audio subsystem.
With this change we can avoid passing the EPLL clock to the ASoC
machine driver.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

This allows clk rate propagation up to the clock tree so EPLL
can be reprogrammed indirectly when setting rate of the Audio
Subsystem clocks.
The advantage is that sound machine driver can operate only
on the leaf clocks rather than explicitly re-configuring
the root clock (EPLL).
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Parent clock of the MAU_EPLL gate clock on exynos5422 is
"mout_user_mau_epll", not "mout_mau_epll_clk". This change
only affects exynos5422/5800.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

The CEC 32K AO Clock is a dual divider with dual counter to provide a more
precise 32768Hz clock for the CEC subsystem from the external xtal.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Switch the aoclk driver to use the new bindings and switch all the
registers access to regmap only.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

On the first revision of the bindings, only the gates + resets were known
in the AO Clock HW, but more registers used to configures AO clock are known
to be spread among the AO register space.
This patch adds a parent node for the entire system control zone for the AO
domain then moves the clock controller as a subnode of the system control
node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Input source 0 of the mmc controllers is not directly xtal, as currently
described in DT. Each controller is fed by a composite clock (the usual
mux, divider and gate). The muxes inputs are the xtal (default) and the
fclk_div clocks. These parents, along with the divider, should be able to
provide the necessary rates for mmc and nand operation.

The input muxes should also be able to take mpll2, mpll3 and gp0_pll but
these are precious clocks, needed for other usage. It is better if the
mmc does not use these them. For this reason, mpll2, mpll3 and gp0_pll is
not listed among the possible parents.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags
while it should have been in the divider flags

Fixes: 3c277c24 ("clk: meson: gxbb: add cts_mclk_i958")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

CLK_DIVIDER_ROUND_CLOSEST was incorrectly put in the hw.init flags
while it should have been in the divider flags

Fixes: 4087bd4b ("clk: meson: gxbb: add cts_amclk")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

The clock controller also includes some reset lines. This patch
implements a reset controller to assert and de-assert these resets.
The reset controller itself is registered early (through
CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot
process (to start the secondary CPU cores).

According to the public S805 datasheet there are two more reset bits
in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by
this patch (as these seem to be unused in Amlogic's vendor Linux kernel
sources and their u-boot tree):
- bit 15: GEN_DIV_SOFT_RESET
- bit 14: SOFT_RESET

All information was taken from the public S805 Datasheet and Amlogic's
vendor GPL kernel sources. This patch is based on an earlier version
submitted by Carlo Caione.
Suggested-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

This patchadds the clock binding entry for the CEC 32K AO Clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Add the clkids for the clocks feeding the input0 of the mmc controllers
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed (none on this
particular controller at the moment)
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

gxbb clock driver gracefully handles case where the clkid is defined but
the clock hw pointer is not provided, as long as it is not at the end of
the hw_onecell_data array.

This patch ensure that the last entries are defined as well to handle
this particular case.

Fixes: a70c6e06 ("clk: meson: gxbb: protect against holes in the onecell_data array")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

meson8b clock driver gracefully handles case where the clkid is defined
but the clock hw pointer is not provided, as long as it is not at the end
of the hw_onecell_data array.

This patch ensure that the last entries are defined as well to handle
this particular case.

Fixes: e92f7cca ("clk: meson8b: clean up fixed rate clocks")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.

Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Fixes: 0577e485 ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should prevent any system hangs
resulting from cpufreq changes to the clk.
Reported-by: Ondrej Jirman <megous@megous.com>
Fixes: 0577e485 ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>

This SoC is too old.  It is difficult to maintain any longer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

* clk-fixes:
  clk: keystone: sci-clk: Fix sci_clk_get
  clk: meson: mpll: fix mpll0 fractional part ignored
  clk: samsung: exynos5420: The EPLL rate table corrections
  clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock

Currently a bug in the sci_clk_get implementation causes it to always
return a clock belonging to the last device in the static list of clock
data. This is due to a bug in the init code that causes the array
used by sci_clk_get to only be populated with the clocks for the last
device, as each device overwrites the entire array with its own clocks.

Fix this by calculating the actual number of clocks for the SoC, and
allocating the whole array in one go. Also, we don't need the handle
to the init data array anymore after doing this, instead we can
just compare the dev_id / clk_id against the registered clocks and
use binary search for speed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Dave Gerlach <d-gerlach@ti.com>
Fixes: b745c079 ("clk: keystone: Add sci-clk driver support")
Cc: Nishanth Menon <nm@ti.com>
Tested-by: Franklin Cooper <fcooper@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Merge tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes

Pull one Allwinner clock fix from Chen-Yu Tsai:

One critical clock fix for sun5i (A10s/A13/R8) which enables propagation
of clock rate changes from the "cpu" clock to it's parent PLL clock.
This fixes cpufreq related crashes that have been observed on KernelCI
with the C.H.I.P. and multi_v7_defconfig.

* tag 'sunxi-clk-fixes-for-4.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun5i: Add clk_set_rate_parent to the CPU clock

Pull one Meson clock fix from Neil Armstrong

* tag 'meson-clk-fixes-for-4.13-rc4-v2' of git://github.com/baylibre/clk-meson:
  clk: meson: mpll: fix mpll0 fractional part ignored

mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider

Fixes: 007e6e5c ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Currently ccu_frac_helper_set_rate() doesn't wait for a lock bit to be
set before returning. Because of that, unstable clock may be used.

Add a wait for lock in the helper function.

Fixes: 89a3dfb7 ("clk: sunxi-ng: Add fractional lib")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

ccu_frac_helper_read_rate() prints some info which is not really
helpful except during debugging.

Replace printk() with pr_debug().

Fixes: 89a3dfb7 ("clk: sunxi-ng: Add fractional lib")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Driver for multiplier clock is missing a call to
ccu_frac_helper_enable() when fractional mode is selected.

Add a call to ccu_frac_helper_enable().

Fixes: d77e8135 ("clk: sunxi-ng: multiplier: Add fractional support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

N-M factor clock driver is missing a call to ccu_frac_helper_enable()
when fractional mode is used. Additionally, most SoCs require that M
factor must be set to 0 when fractional mode is used.

Without this patch, clock keeps the old value and clk_set_rate() returns
without error.

Fixes: 6174a1e2 ("clk: sunxi-ng: Add N-M-factor clock support")
CC: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>

This patch fixes values of the EPLL K coefficient and changes
the EPLL output frequency values to match exactly what is
possible to achieve with given M, P, S, K coefficients.
This allows to avoid rounding errors and unexpected frequency
being set with clk_set_rate(), due to recalc_rate returning
different values than the PLL rate specified in the
exynos5420_epll_24mhz_tbl table. E.g. this prevents a case
where two consecutive clk_set_rate() calls with same argument
result in different PLL output frequency.

The PLL output frequencies have been calculated with formula:

f = fxtal * (M * 2^16 + K) / (P * 2^S) / 2^16

where fxtal = 24000000.

Fixes: 9842452a ("clk: samsung: exynos542x: Add EPLL rate table")
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

The Amlogic Meson8/Meson8b/Meson8m2 clock controller provides some reset
lines. These are used for example to boot the secondary CPU cores.

This patch describes the reset controller which is embedded into the
clock controller on these SoCs.
A header file is provided which provides preprocessor macros for each
reset line (to make the .dts files easier to read).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Remove trailing extra underscore in definition of _CCU_SUN8I_R_H
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The current CPU clock is missing the option to change the rate of its
parents, leading to improper rates calculated by cpufreq, and eventually
crashes.

Cc: <stable@vger.kernel.org>
Fixes: 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver")
Reported-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>